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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>x86 and amd64 instruction reference</title></head><body><h1>x86 and amd64 instruction reference</h1><p>Derived from the December 2023 version of the <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a>. Last updated 2024-02-18.</p><p><strong>THIS REFERENCE IS NOT PERFECT.</strong> It's been mechanically separated into distinct files by a
dumb script. It may be enough to replace the official documentation on your weekend reverse engineering
project, but for anything where money is at stake, go get the official and freely available documentation.
</p><h2>Core Instructions</h2><table><tr><th>Mnemonic</th><th>Summary</th></tr><tr><td><a href='aaa.html'>AAA</a></td><td>ASCII Adjust After Addition</td></tr><tr><td><a href='aad.html'>AAD</a></td><td>ASCII Adjust AX Before Division</td></tr><tr><td><a href='aam.html'>AAM</a></td><td>ASCII Adjust AX After Multiply</td></tr><tr><td><a href='aas.html'>AAS</a></td><td>ASCII Adjust AL After Subtraction</td></tr><tr><td><a href='adc.html'>ADC</a></td><td>Add With Carry</td></tr><tr><td><a href='adcx.html'>ADCX</a></td><td>Unsigned Integer Addition of Two Operands With Carry Flag</td></tr><tr><td><a href='add.html'>ADD</a></td><td>Add</td></tr><tr><td><a href='addpd.html'>ADDPD</a></td><td>Add Packed Double Precision Floating-Point Values</td></tr><tr><td><a href='addps.html'>ADDPS</a></td><td>Add Packed Single Precision Floating-Point Values</td></tr><tr><td><a href='addsd.html'>ADDSD</a></td><td>Add Scalar Double Precision Floating-Point Values</td></tr><tr><td><a href='addss.html'>ADDSS</a></td><td>Add Scalar Single Precision Floating-Point Values</td></tr><tr><td><a href='addsubpd.html'>ADDSUBPD</a></td><td>Packed Double Precision Floating-Point Add/Subtract</td></tr><tr><td><a href='addsubps.html'>ADDSUBPS</a></td><td>Packed Single Precision Floating-Point Add/Subtract</td></tr><tr><td><a href='adox.html'>ADOX</a></td><td>Unsigned Integer Addition of Two Operands With Overflow Flag</td></tr><tr><td><a href='aesdec.html'>AESDEC</a></td><td>Perform One Round of an AES Decryption Flow</td></tr><tr><td><a href='aesdec128kl.html'>AESDEC128KL</a></td><td>Perform Ten Rounds of AES Decryption Flow With Key Locker Using 128-BitKey</td></tr><tr><td><a href='aesdec256kl.html'>AESDEC256KL</a></td><td>Perform 14 Rounds of AES Decryption Flow With Key Locker Using 256-Bit Key</td></tr><tr><td><a href='aesdeclast.html'>AESDECLAST</a></td><td>Perform Last Round of an AES Decryption Flow</td></tr><tr><td><a href='aesdecwide128kl.html'>AESDECWIDE128KL</a></td><td>Perform Ten Rounds of AES Decryption Flow With Key Locker on 8 BlocksUsing 128-Bit Key</td></tr><tr><td><a href='aesdecwide256kl.html'>AESDECWIDE256KL</a></td><td>Perform 14 Rounds of AES Decryption Flow With Key Locker on 8 BlocksUsing 256-Bit Key</td></tr><tr><td><a href='aesenc.html'>AESENC</a></td><td>Perform One Round of an AES Encryption Flow</td></tr><tr><td><a href='aesenc128kl.html'>AESENC128KL</a></td><td>Perform Ten Rounds of AES Encryption Flow With Key Locker Using 128-Bit Key</td></tr><tr><td><a href='aesenc256kl.html'>AESENC256KL</a></td><td>Perform 14 Rounds of AES Encryption Flow With Key Locker Using 256-Bit Key</td></tr><tr><td><a href='aesenclast.html'>AESENCLAST</a></td><td>Perform Last Round of an AES Encryption Flow</td></tr><tr><td><a href='aesencwide128kl.html'>AESENCWIDE128KL</a></td><td>Perform Ten Rounds of AES Encryption Flow With Key Locker on 8 BlocksUsing 128-Bit Key</td></tr><tr><td><a href='aesencwide256kl.html'>AESENCWIDE256KL</a></td><td>Perform 14 Rounds of AES Encryption Flow With Key Locker on 8 BlocksUsing 256-Bit Key</td></tr><tr><td><a href='aesimc.html'>AESIMC</a></td><td>Perform the AES InvMixColumn Transformation</td></tr><tr><td><a href='aeskeygenassist.html'>AESKEYGENASSIST</a></td><td>AES Round Key Generation Assist</td></tr><tr><td><a href='and.html'>AND</a></td><td>Logical AND</td></tr><tr><td><a href='andn.html'>ANDN</a></td><td>Logical AND NOT</td></tr><tr><td><a href='andnpd.html'>ANDNPD</a></td><td>Bitwise Logical AND NOT of Packed Double Precision Floating-Point Values</td></tr><tr><td><a href='andnps.html'>ANDNPS</a></td><td>Bitwise Logical AND NOT of Packed Single Precision Floating-Point Values</td></tr><tr><td><a href='andpd.html'>ANDPD</a></td><td>Bitwise Logical AND of Packed Double Precision Floating-Point Values</td></tr><tr><td><a href='andps.html'>ANDPS</a></td><td>Bitwise Logical AND of Packed Single Precision Floating-Point Values</td></tr><tr><td><a href='arpl.html'>ARPL</a></td><td>Adjust RPL Field of Segment Selector</td></tr><tr><td><a href='bextr.html'>BEXTR</a></td><td>Bit Field Extract</td></tr><tr><td><a href='blendpd.html'>BLENDPD</a></td><td>Blend Packed Double Precision Floating-Point Values</td></tr><tr><td><a href='blendps.html'>BLENDPS</a></td><td>Blend Packed Single Precision Floating-Point Values</td></tr><tr><td><a href='blendvpd.html'>BLENDVPD</a></td><td>Variable Blend Packed Double Precision Floating-Point Values</td></tr><tr><td><a href='blendvps.html'>BLENDVPS</a></td><td>Variable Blend Packed Single Precision Floating-Point Values</td></tr><tr><td><a href='blsi.html'>BLSI</a></td><td>Extract Lowest Set Isolated Bit</td></tr><tr><td><a href='blsmsk.html'>BLSMSK</a></td><td>Get Mask Up to Lowest Set Bit</td></tr><tr><td><a href='blsr.html'>BLSR</a></td><td>Reset Lowest Set Bit</td></tr><tr><td><a href='bndcl.html'>BNDCL</a></td><td>Check Lower Bound</td></tr><tr><td><a href='bndcu.bndcn.html'>BNDCN</a></td><td>Check Upper Bound</td></tr><tr><td><a href='bndcu.bndcn.html'>BNDCU</a></td><td>Check Upper Bound</td></tr><tr><td><a href='bndldx.html'>BNDLDX</a></td><td>Load Extended Bounds Using Address Translation</td></tr><tr><td><a href='bndmk.html'>BNDMK</a></td><td>Make Bounds</td></tr><tr><td><a href='bndmov.html'>BNDMOV</a></td><td>Move Bounds</td></tr><tr><td><a href='bndstx.html'>BNDSTX</a></td><td>Store Extended Bounds Using Address Translation</td></tr><tr><td><a href='bound.html'>BOUND</a></td><td>Check Array Index Against Bounds</td></tr><tr><td><a href='bsf.html'>BSF</a></td><td>Bit Scan Forward</td></tr><tr><td><a href='bsr.html'>BSR</a></td><td>Bit Scan Reverse</td></tr><tr><td><a href='bswap.html'>BSWAP</a></td><td>Byte Swap</td></tr><tr><td><a href='bt.html'>BT</a></td><td>Bit Test</td></tr><tr><td><a href='btc.html'>BTC</a></td><td>Bit Test and Complement</td></tr><tr><td><a href='btr.html'>BTR</a></td><td>Bit Test and Reset</td></tr><tr><td><a href='bts.html'>BTS</a></td><td>Bit Test and Set</td></tr><tr><td><a href='bzhi.html'>BZHI</a></td><td>Zero High Bits Starting with Specified Bit Position</td></tr><tr><td><a href='call.html'>CALL</a></td><td>Call Procedure</td></tr><tr><td><a href='cbw.cwde.cdqe.html'>CBW</a></td><td>Convert Byte to Word/Convert Word to Doubleword/Convert Doubleword toQuadword</td></tr><tr><td><a href='cwd.cdq.cqo.html'>CDQ</a></td><td>Convert Word to Doubleword/Convert Doubleword to Quadword</td></tr><tr><td><a href='cbw.cwde.cdqe.html'>CDQE</a></td><td>Convert Byte to Word/Convert Word to Doubleword/Convert Doubleword toQuadword</td></tr><tr><td><a href='clac.html'>CLAC</a></td><td>Clear AC Flag in EFLAGS Register</td></tr><tr><td><a href='clc.html'>CLC</a></td><td>Clear Carry Flag</td></tr><tr><td><a href='cld.html'>CLD</a></td><td>Clear Direction Flag</td></tr><tr><td><a href='cldemote.html'>CLDEMOTE</a></td><td>Cache Line Demote</td></tr><tr><td><a href='clflush.html'>CLFLUSH</a></td><td>Flush Cache Line</td></tr><tr><td><a href='clflushopt.html'>CLFLUSHOPT</a></td><td>Flush Cache Line Optimized</td></tr><tr><td><a href='cli.html'>CLI</a></td><td>Clear Interrupt Flag</td></tr><tr><td><a href='clrssbsy.html'>CLRSSBSY</a></td><td>Clear Busy Flag in a Supervisor Shadow Stack Token</td></tr><tr><td><a href='clts.html'>CLTS</a></td><td>Clear Task-Switched Flag in CR0</td></tr><tr><td><a href='clui.html'>CLUI</a></td><td>Clear User Interrupt Flag</td></tr><tr><td><a href='clwb.html'>CLWB</a></td><td>Cache Line Write Back</td></tr><tr><td><a href='cmc.html'>CMC</a></td><td>Complement Carry Flag</td></tr><tr><td><a href='cmovcc.html'>CMOVcc</a></td><td>Conditional Move</td></tr><tr><td><a href='cmp.html'>CMP</a></td><td>Compare Two Operands</td></tr><tr><td><a href='cmppd.html'>CMPPD</a></td><td>Compare Packed Double Precision Floating-Point Values</td></tr><tr><td><a href='cmpps.html'>CMPPS</a></td><td>Compare Packed Single Precision Floating-Point Values</td></tr><tr><td><a href='cmps.cmpsb.cmpsw.cmpsd.cmpsq.html'>CMPS</a></td><td>Compare String Operands</td></tr><tr><td><a href='cmps.cmpsb.cmpsw.cmpsd.cmpsq.html'>CMPSB</a></td><td>Compare String Operands</td></tr><tr><td><a href='cmps.cmpsb.cmpsw.cmpsd.cmpsq.html'>CMPSD</a></td><td>Compare String Operands</td></tr><tr><td><a href='cmpsd.html'>CMPSD</a> (1)</td><td>Compare Scalar Double Precision Floating-Point Value</td></tr><tr><td><a href='cmps.cmpsb.cmpsw.cmpsd.cmpsq.html'>CMPSQ</a></td><td>Compare String Operands</td></tr><tr><td><a href='cmpss.html'>CMPSS</a></td><td>Compare Scalar Single Precision Floating-Point Value</td></tr><tr><td><a href='cmps.cmpsb.cmpsw.cmpsd.cmpsq.html'>CMPSW</a></td><td>Compare String Operands</td></tr><tr><td><a href='cmpxchg.html'>CMPXCHG</a></td><td>Compare and Exchange</td></tr><tr><td><a href='cmpxchg8b.cmpxchg16b.html'>CMPXCHG16B</a></td><td>Compare and Exchange Bytes</td></tr><tr><td><a href='cmpxchg8b.cmpxchg16b.html'>CMPXCHG8B</a></td><td>Compare and Exchange Bytes</td></tr><tr><td><a href='comisd.html'>COMISD</a></td><td>Compare Scalar Ordered Double Precision Floating-Point Values and Set EFLAGS</td></tr><tr><td><a href='comiss.html'>COMISS</a></td><td>Compare Scalar Ordered Single Precision Floating-Point Values and Set EFLAGS</td></tr><tr><td><a href='cpuid.html'>CPUID</a></td><td>CPU Identification</td></tr><tr><td><a href='cwd.cdq.cqo.html'>CQO</a></td><td>Convert Word to Doubleword/Convert Doubleword to Quadword</td></tr><tr><td><a href='crc32.html'>CRC32</a></td><td>Accumulate CRC32 Value</td></tr><tr><td><a href='cvtdq2pd.html'>CVTDQ2PD</a></td><td>Convert Packed Doubleword Integers to Packed Double Precision Floating-PointValues</td></tr><tr><td><a href='cvtdq2ps.html'>CVTDQ2PS</a></td><td>Convert Packed Doubleword Integers to Packed Single Precision Floating-PointValues</td></tr><tr><td><a href='cvtpd2dq.html'>CVTPD2DQ</a></td><td>Convert Packed Double Precision Floating-Point Values to Packed DoublewordIntegers</td></tr><tr><td><a href='cvtpd2pi.html'>CVTPD2PI</a></td><td>Convert Packed Double Precision Floating-Point Values to Packed Dword Integers</td></tr><tr><td><a href='cvtpd2ps.html'>CVTPD2PS</a></td><td>Convert Packed Double Precision Floating-Point Values to Packed Single PrecisionFloating-Point Values</td></tr><tr><td><a href='cvtpi2pd.html'>CVTPI2PD</a></td><td>Convert Packed Dword Integers to Packed Double Precision Floating-Point Values</td></tr><tr><td><a href='cvtpi2ps.html'>CVTPI2PS</a></td><td>Convert Packed Dword Integers to Packed Single Precision Floating-Point Values</td></tr><tr><td><a href='cvtps2dq.html'>CVTPS2DQ</a></td><td>Convert Packed Single Precision Floating-Point Values to Packed SignedDoubleword Integer Values</td></tr><tr><td><a href='cvtps2pd.html'>CVTPS2PD</a></td><td>Convert Packed Single Precision Floating-Point Values to Packed Double PrecisionFloating-Point Values</td></tr><tr><td><a href='cvtps2pi.html'>CVTPS2PI</a></td><td>Convert Packed Single Precision Floating-Point Values to Packed Dword Integers</td></tr><tr><td><a href='cvtsd2si.html'>CVTSD2SI</a></td><td>Convert Scalar Double Precision Floating-Point Value to Doubleword Integer</td></tr><tr><td><a href='cvtsd2ss.html'>CVTSD2SS</a></td><td>Convert Scalar Double Precision Floating-Point Value to Scalar Single PrecisionFloating-Point Value</td></tr><tr><td><a href='cvtsi2sd.html'>CVTSI2SD</a></td><td>Convert Doubleword Integer to Scalar Double Precision Floating-Point Value</td></tr><tr><td><a href='cvtsi2ss.html'>CVTSI2SS</a></td><td>Convert Doubleword Integer to Scalar Single Precision Floating-Point Value</td></tr><tr><td><a href='cvtss2sd.html'>CVTSS2SD</a></td><td>Convert Scalar Single Precision Floating-Point Value to Scalar Double PrecisionFloating-Point Value</td></tr><tr><td><a href='cvtss2si.html'>CVTSS2SI</a></td><td>Convert Scalar Single Precision Floating-Point Value to Doubleword Integer</td></tr><tr><td><a href='cvttpd2dq.html'>CVTTPD2DQ</a></td><td>Convert with Truncation Packed Double Precision Floating-Point Values toPacked Doubleword Integers</td></tr><tr><td><a href='cvttpd2pi.html'>CVTTPD2PI</a></td><td>Convert With Truncation Packed Double Precision Floating-Point Values to PackedDword Integers</td></tr><tr><td><a href='cvttps2dq.html'>CVTTPS2DQ</a></td><td>Convert With Truncation Packed Single Precision Floating-Point Values to PackedSigned Doubleword Integer Values</td></tr><tr><td><a href='cvttps2pi.html'>CVTTPS2PI</a></td><td>Convert With Truncation Packed Single Precision Floating-Point Values to PackedDword Integers</td></tr><tr><td><a href='cvttsd2si.html'>CVTTSD2SI</a></td><td>Convert With Truncation Scalar Double Precision Floating-Point Value to SignedInteger</td></tr><tr><td><a href='cvttss2si.html'>CVTTSS2SI</a></td><td>Convert With Truncation Scalar Single Precision Floating-Point Value to Integer</td></tr><tr><td><a href='cwd.cdq.cqo.html'>CWD</a></td><td>Convert Word to Doubleword/Convert Doubleword to Quadword</td></tr><tr><td><a href='cbw.cwde.cdqe.html'>CWDE</a></td><td>Convert Byte to Word/Convert Word to Doubleword/Convert Doubleword toQuadword</td></tr><tr><td><a href='daa.html'>DAA</a></td><td>Decimal Adjust AL After Addition</td></tr><tr><td><a href='das.html'>DAS</a></td><td>Decimal Adjust AL After Subtraction</td></tr><tr><td><a href='dec.html'>DEC</a></td><td>Decrement by 1</td></tr><tr><td><a href='div.html'>DIV</a></td><td>Unsigned Divide</td></tr><tr><td><a href='divpd.html'>DIVPD</a></td><td>Divide Packed Double Precision Floating-Point Values</td></tr><tr><td><a href='divps.html'>DIVPS</a></td><td>Divide Packed Single Precision Floating-Point Values</td></tr><tr><td><a href='divsd.html'>DIVSD</a></td><td>Divide Scalar Double Precision Floating-Point Value</td></tr><tr><td><a href='divss.html'>DIVSS</a></td><td>Divide Scalar Single Precision Floating-Point Values</td></tr><tr><td><a href='dppd.html'>DPPD</a></td><td>Dot Product of Packed Double Precision Floating-Point Values</td></tr><tr><td><a href='dpps.html'>DPPS</a></td><td>Dot Product of Packed Single Precision Floating-Point Values</td></tr><tr><td><a href='emms.html'>EMMS</a></td><td>Empty MMX Technology State</td></tr><tr><td><a href='encodekey128.html'>ENCODEKEY128</a></td><td>Encode 128-Bit Key With Key Locker</td></tr><tr><td><a href='encodekey256.html'>ENCODEKEY256</a></td><td>Encode 256-Bit Key With Key Locker</td></tr><tr><td><a href='endbr32.html'>ENDBR32</a></td><td>Terminate an Indirect Branch in 32-bit and Compatibility Mode</td></tr><tr><td><a href='endbr64.html'>ENDBR64</a></td><td>Terminate an Indirect Branch in 64-bit Mode</td></tr><tr><td><a href='enqcmd.html'>ENQCMD</a></td><td>Enqueue Command</td></tr><tr><td><a href='enqcmds.html'>ENQCMDS</a></td><td>Enqueue Command Supervisor</td></tr><tr><td><a href='enter.html'>ENTER</a></td><td>Make Stack Frame for Procedure Parameters</td></tr><tr><td><a href='extractps.html'>EXTRACTPS</a></td><td>Extract Packed Floating-Point Values</td></tr><tr><td><a href='f2xm1.html'>F2XM1</a></td><td>Compute 2x–1</td></tr><tr><td><a href='fabs.html'>FABS</a></td><td>Absolute Value</td></tr><tr><td><a href='fadd.faddp.fiadd.html'>FADD</a></td><td>Add</td></tr><tr><td><a href='fadd.faddp.fiadd.html'>FADDP</a></td><td>Add</td></tr><tr><td><a href='fbld.html'>FBLD</a></td><td>Load Binary Coded Decimal</td></tr><tr><td><a href='fbstp.html'>FBSTP</a></td><td>Store BCD Integer and Pop</td></tr><tr><td><a href='fchs.html'>FCHS</a></td><td>Change Sign</td></tr><tr><td><a href='fclex.fnclex.html'>FCLEX</a></td><td>Clear Exceptions</td></tr><tr><td><a href='fcmovcc.html'>FCMOVcc</a></td><td>Floating-Point Conditional Move</td></tr><tr><td><a href='fcom.fcomp.fcompp.html'>FCOM</a></td><td>Compare Floating-Point Values</td></tr><tr><td><a href='fcomi.fcomip.fucomi.fucomip.html'>FCOMI</a></td><td>Compare Floating-Point Values and Set EFLAGS</td></tr><tr><td><a href='fcomi.fcomip.fucomi.fucomip.html'>FCOMIP</a></td><td>Compare Floating-Point Values and Set EFLAGS</td></tr><tr><td><a href='fcom.fcomp.fcompp.html'>FCOMP</a></td><td>Compare Floating-Point Values</td></tr><tr><td><a href='fcom.fcomp.fcompp.html'>FCOMPP</a></td><td>Compare Floating-Point Values</td></tr><tr><td><a href='fcos.html'>FCOS</a></td><td>Cosine</td></tr><tr><td><a href='fdecstp.html'>FDECSTP</a></td><td>Decrement Stack-Top Pointer</td></tr><tr><td><a href='fdiv.fdivp.fidiv.html'>FDIV</a></td><td>Divide</td></tr><tr><td><a href='fdiv.fdivp.fidiv.html'>FDIVP</a></td><td>Divide</td></tr><tr><td><a href='fdivr.fdivrp.fidivr.html'>FDIVR</a></td><td>Reverse Divide</td></tr><tr><td><a href='fdivr.fdivrp.fidivr.html'>FDIVRP</a></td><td>Reverse Divide</td></tr><tr><td><a href='ffree.html'>FFREE</a></td><td>Free Floating-Point Register</td></tr><tr><td><a href='fadd.faddp.fiadd.html'>FIADD</a></td><td>Add</td></tr><tr><td><a href='ficom.ficomp.html'>FICOM</a></td><td>Compare Integer</td></tr><tr><td><a href='ficom.ficomp.html'>FICOMP</a></td><td>Compare Integer</td></tr><tr><td><a href='fdiv.fdivp.fidiv.html'>FIDIV</a></td><td>Divide</td></tr><tr><td><a href='fdivr.fdivrp.fidivr.html'>FIDIVR</a></td><td>Reverse Divide</td></tr><tr><td><a href='fild.html'>FILD</a></td><td>Load Integer</td></tr><tr><td><a href='fmul.fmulp.fimul.html'>FIMUL</a></td><td>Multiply</td></tr><tr><td><a href='fincstp.html'>FINCSTP</a></td><td>Increment Stack-Top Pointer</td></tr><tr><td><a href='finit.fninit.html'>FINIT</a></td><td>Initialize Floating-Point Unit</td></tr><tr><td><a href='fist.fistp.html'>FIST</a></td><td>Store Integer</td></tr><tr><td><a href='fist.fistp.html'>FISTP</a></td><td>Store Integer</td></tr><tr><td><a href='fisttp.html'>FISTTP</a></td><td>Store Integer With Truncation</td></tr><tr><td><a href='fsub.fsubp.fisub.html'>FISUB</a></td><td>Subtract</td></tr><tr><td><a href='fsubr.fsubrp.fisubr.html'>FISUBR</a></td><td>Reverse Subtract</td></tr><tr><td><a href='fld.html'>FLD</a></td><td>Load Floating-Point Value</td></tr><tr><td><a href='fld1.fldl2t.fldl2e.fldpi.fldlg2.fldln2.fldz.html'>FLD1</a></td><td>Load Constant</td></tr><tr><td><a href='fldcw.html'>FLDCW</a></td><td>Load x87 FPU Control Word</td></tr><tr><td><a href='fldenv.html'>FLDENV</a></td><td>Load x87 FPU Environment</td></tr><tr><td><a href='fld1.fldl2t.fldl2e.fldpi.fldlg2.fldln2.fldz.html'>FLDL2E</a></td><td>Load Constant</td></tr><tr><td><a href='fld1.fldl2t.fldl2e.fldpi.fldlg2.fldln2.fldz.html'>FLDL2T</a></td><td>Load Constant</td></tr><tr><td><a href='fld1.fldl2t.fldl2e.fldpi.fldlg2.fldln2.fldz.html'>FLDLG2</a></td><td>Load Constant</td></tr><tr><td><a href='fld1.fldl2t.fldl2e.fldpi.fldlg2.fldln2.fldz.html'>FLDLN2</a></td><td>Load Constant</td></tr><tr><td><a href='fld1.fldl2t.fldl2e.fldpi.fldlg2.fldln2.fldz.html'>FLDPI</a></td><td>Load Constant</td></tr><tr><td><a href='fld1.fldl2t.fldl2e.fldpi.fldlg2.fldln2.fldz.html'>FLDZ</a></td><td>Load Constant</td></tr><tr><td><a href='fmul.fmulp.fimul.html'>FMUL</a></td><td>Multiply</td></tr><tr><td><a href='fmul.fmulp.fimul.html'>FMULP</a></td><td>Multiply</td></tr><tr><td><a href='fclex.fnclex.html'>FNCLEX</a></td><td>Clear Exceptions</td></tr><tr><td><a href='finit.fninit.html'>FNINIT</a></td><td>Initialize Floating-Point Unit</td></tr><tr><td><a href='fnop.html'>FNOP</a></td><td>No Operation</td></tr><tr><td><a href='fsave.fnsave.html'>FNSAVE</a></td><td>Store x87 FPU State</td></tr><tr><td><a href='fstcw.fnstcw.html'>FNSTCW</a></td><td>Store x87 FPU Control Word</td></tr><tr><td><a href='fstenv.fnstenv.html'>FNSTENV</a></td><td>Store x87 FPU Environment</td></tr><tr><td><a href='fstsw.fnstsw.html'>FNSTSW</a></td><td>Store x87 FPU Status Word</td></tr><tr><td><a href='fpatan.html'>FPATAN</a></td><td>Partial Arctangent</td></tr><tr><td><a href='fprem.html'>FPREM</a></td><td>Partial Remainder</td></tr><tr><td><a href='fprem1.html'>FPREM1</a></td><td>Partial Remainder</td></tr><tr><td><a href='fptan.html'>FPTAN</a></td><td>Partial Tangent</td></tr><tr><td><a href='frndint.html'>FRNDINT</a></td><td>Round to Integer</td></tr><tr><td><a href='frstor.html'>FRSTOR</a></td><td>Restore x87 FPU State</td></tr><tr><td><a href='fsave.fnsave.html'>FSAVE</a></td><td>Store x87 FPU State</td></tr><tr><td><a href='fscale.html'>FSCALE</a></td><td>Scale</td></tr><tr><td><a href='fsin.html'>FSIN</a></td><td>Sine</td></tr><tr><td><a href='fsincos.html'>FSINCOS</a></td><td>Sine and Cosine</td></tr><tr><td><a href='fsqrt.html'>FSQRT</a></td><td>Square Root</td></tr><tr><td><a href='fst.fstp.html'>FST</a></td><td>Store Floating-Point Value</td></tr><tr><td><a href='fstcw.fnstcw.html'>FSTCW</a></td><td>Store x87 FPU Control Word</td></tr><tr><td><a href='fstenv.fnstenv.html'>FSTENV</a></td><td>Store x87 FPU Environment</td></tr><tr><td><a href='fst.fstp.html'>FSTP</a></td><td>Store Floating-Point Value</td></tr><tr><td><a href='fstsw.fnstsw.html'>FSTSW</a></td><td>Store x87 FPU Status Word</td></tr><tr><td><a href='fsub.fsubp.fisub.html'>FSUB</a></td><td>Subtract</td></tr><tr><td><a href='fsub.fsubp.fisub.html'>FSUBP</a></td><td>Subtract</td></tr><tr><td><a href='fsubr.fsubrp.fisubr.html'>FSUBR</a></td><td>Reverse Subtract</td></tr><tr><td><a href='fsubr.fsubrp.fisubr.html'>FSUBRP</a></td><td>Reverse Subtract</td></tr><tr><td><a href='ftst.html'>FTST</a></td><td>TEST</td></tr><tr><td><a href='fucom.fucomp.fucompp.html'>FUCOM</a></td><td>Unordered Compare Floating-Point Values</td></tr><tr><td><a href='fcomi.fcomip.fucomi.fucomip.html'>FUCOMI</a></td><td>Compare Floating-Point Values and Set EFLAGS</td></tr><tr><td><a href='fcomi.fcomip.fucomi.fucomip.html'>FUCOMIP</a></td><td>Compare Floating-Point Values and Set EFLAGS</td></tr><tr><td><a href='fucom.fucomp.fucompp.html'>FUCOMP</a></td><td>Unordered Compare Floating-Point Values</td></tr><tr><td><a href='fucom.fucomp.fucompp.html'>FUCOMPP</a></td><td>Unordered Compare Floating-Point Values</td></tr><tr><td><a href='wait.fwait.html'>FWAIT</a></td><td>Wait</td></tr><tr><td><a href='fxam.html'>FXAM</a></td><td>Examine Floating-Point</td></tr><tr><td><a href='fxch.html'>FXCH</a></td><td>Exchange Register Contents</td></tr><tr><td><a href='fxrstor.html'>FXRSTOR</a></td><td>Restore x87 FPU, MMX, XMM, and MXCSR State</td></tr><tr><td><a href='fxsave.html'>FXSAVE</a></td><td>Save x87 FPU, MMX Technology, and SSE State</td></tr><tr><td><a href='fxtract.html'>FXTRACT</a></td><td>Extract Exponent and Significand</td></tr><tr><td><a href='fyl2x.html'>FYL2X</a></td><td>Compute y ∗ log2x</td></tr><tr><td><a href='fyl2xp1.html'>FYL2XP1</a></td><td>Compute y ∗ log2(x +1)</td></tr><tr><td><a href='gf2p8affineinvqb.html'>GF2P8AFFINEINVQB</a></td><td>Galois Field Affine Transformation Inverse</td></tr><tr><td><a href='gf2p8affineqb.html'>GF2P8AFFINEQB</a></td><td>Galois Field Affine Transformation</td></tr><tr><td><a href='gf2p8mulb.html'>GF2P8MULB</a></td><td>Galois Field Multiply Bytes</td></tr><tr><td><a href='haddpd.html'>HADDPD</a></td><td>Packed Double Precision Floating-Point Horizontal Add</td></tr><tr><td><a href='haddps.html'>HADDPS</a></td><td>Packed Single Precision Floating-Point Horizontal Add</td></tr><tr><td><a href='hlt.html'>HLT</a></td><td>Halt</td></tr><tr><td><a href='hreset.html'>HRESET</a></td><td>History Reset</td></tr><tr><td><a href='hsubpd.html'>HSUBPD</a></td><td>Packed Double Precision Floating-Point Horizontal Subtract</td></tr><tr><td><a href='hsubps.html'>HSUBPS</a></td><td>Packed Single Precision Floating-Point Horizontal Subtract</td></tr><tr><td><a href='idiv.html'>IDIV</a></td><td>Signed Divide</td></tr><tr><td><a href='imul.html'>IMUL</a></td><td>Signed Multiply</td></tr><tr><td><a href='in.html'>IN</a></td><td>Input From Port</td></tr><tr><td><a href='inc.html'>INC</a></td><td>Increment by 1</td></tr><tr><td><a href='incsspd.incsspq.html'>INCSSPD</a></td><td>Increment Shadow Stack Pointer</td></tr><tr><td><a href='incsspd.incsspq.html'>INCSSPQ</a></td><td>Increment Shadow Stack Pointer</td></tr><tr><td><a href='ins.insb.insw.insd.html'>INS</a></td><td>Input from Port to String</td></tr><tr><td><a href='ins.insb.insw.insd.html'>INSB</a></td><td>Input from Port to String</td></tr><tr><td><a href='ins.insb.insw.insd.html'>INSD</a></td><td>Input from Port to String</td></tr><tr><td><a href='insertps.html'>INSERTPS</a></td><td>Insert Scalar Single Precision Floating-Point Value</td></tr><tr><td><a href='ins.insb.insw.insd.html'>INSW</a></td><td>Input from Port to String</td></tr><tr><td><a href='intn.into.int3.int1.html'>INT n</a></td><td>Call to Interrupt Procedure</td></tr><tr><td><a href='intn.into.int3.int1.html'>INT1</a></td><td>Call to Interrupt Procedure</td></tr><tr><td><a href='intn.into.int3.int1.html'>INT3</a></td><td>Call to Interrupt Procedure</td></tr><tr><td><a href='intn.into.int3.int1.html'>INTO</a></td><td>Call to Interrupt Procedure</td></tr><tr><td><a href='invd.html'>INVD</a></td><td>Invalidate Internal Caches</td></tr><tr><td><a href='invlpg.html'>INVLPG</a></td><td>Invalidate TLB Entries</td></tr><tr><td><a href='invpcid.html'>INVPCID</a></td><td>Invalidate Process-Context Identifier</td></tr><tr><td><a href='iret.iretd.iretq.html'>IRET</a></td><td>Interrupt Return</td></tr><tr><td><a href='iret.iretd.iretq.html'>IRETD</a></td><td>Interrupt Return</td></tr><tr><td><a href='iret.iretd.iretq.html'>IRETQ</a></td><td>Interrupt Return</td></tr><tr><td><a href='jmp.html'>JMP</a></td><td>Jump</td></tr><tr><td><a href='jcc.html'>Jcc</a></td><td>Jump if Condition Is Met</td></tr><tr><td><a href='kaddw.kaddb.kaddq.kaddd.html'>KADDB</a></td><td>ADD Two Masks</td></tr><tr><td><a href='kaddw.kaddb.kaddq.kaddd.html'>KADDD</a></td><td>ADD Two Masks</td></tr><tr><td><a href='kaddw.kaddb.kaddq.kaddd.html'>KADDQ</a></td><td>ADD Two Masks</td></tr><tr><td><a href='kaddw.kaddb.kaddq.kaddd.html'>KADDW</a></td><td>ADD Two Masks</td></tr><tr><td><a href='kandw.kandb.kandq.kandd.html'>KANDB</a></td><td>Bitwise Logical AND Masks</td></tr><tr><td><a href='kandw.kandb.kandq.kandd.html'>KANDD</a></td><td>Bitwise Logical AND Masks</td></tr><tr><td><a href='kandnw.kandnb.kandnq.kandnd.html'>KANDNB</a></td><td>Bitwise Logical AND NOT Masks</td></tr><tr><td><a href='kandnw.kandnb.kandnq.kandnd.html'>KANDND</a></td><td>Bitwise Logical AND NOT Masks</td></tr><tr><td><a href='kandnw.kandnb.kandnq.kandnd.html'>KANDNQ</a></td><td>Bitwise Logical AND NOT Masks</td></tr><tr><td><a href='kandnw.kandnb.kandnq.kandnd.html'>KANDNW</a></td><td>Bitwise Logical AND NOT Masks</td></tr><tr><td><a href='kandw.kandb.kandq.kandd.html'>KANDQ</a></td><td>Bitwise Logical AND Masks</td></tr><tr><td><a href='kandw.kandb.kandq.kandd.html'>KANDW</a></td><td>Bitwise Logical AND Masks</td></tr><tr><td><a href='kmovw.kmovb.kmovq.kmovd.html'>KMOVB</a></td><td>Move From and to Mask Registers</td></tr><tr><td><a href='kmovw.kmovb.kmovq.kmovd.html'>KMOVD</a></td><td>Move From and to Mask Registers</td></tr><tr><td><a href='kmovw.kmovb.kmovq.kmovd.html'>KMOVQ</a></td><td>Move From and to Mask Registers</td></tr><tr><td><a href='kmovw.kmovb.kmovq.kmovd.html'>KMOVW</a></td><td>Move From and to Mask Registers</td></tr><tr><td><a href='knotw.knotb.knotq.knotd.html'>KNOTB</a></td><td>NOT Mask Register</td></tr><tr><td><a href='knotw.knotb.knotq.knotd.html'>KNOTD</a></td><td>NOT Mask Register</td></tr><tr><td><a href='knotw.knotb.knotq.knotd.html'>KNOTQ</a></td><td>NOT Mask Register</td></tr><tr><td><a href='knotw.knotb.knotq.knotd.html'>KNOTW</a></td><td>NOT Mask Register</td></tr><tr><td><a href='korw.korb.korq.kord.html'>KORB</a></td><td>Bitwise Logical OR Masks</td></tr><tr><td><a href='korw.korb.korq.kord.html'>KORD</a></td><td>Bitwise Logical OR Masks</td></tr><tr><td><a href='korw.korb.korq.kord.html'>KORQ</a></td><td>Bitwise Logical OR Masks</td></tr><tr><td><a href='kortestw.kortestb.kortestq.kortestd.html'>KORTESTB</a></td><td>OR Masks and Set Flags</td></tr><tr><td><a href='kortestw.kortestb.kortestq.kortestd.html'>KORTESTD</a></td><td>OR Masks and Set Flags</td></tr><tr><td><a href='kortestw.kortestb.kortestq.kortestd.html'>KORTESTQ</a></td><td>OR Masks and Set Flags</td></tr><tr><td><a href='kortestw.kortestb.kortestq.kortestd.html'>KORTESTW</a></td><td>OR Masks and Set Flags</td></tr><tr><td><a href='korw.korb.korq.kord.html'>KORW</a></td><td>Bitwise Logical OR Masks</td></tr><tr><td><a href='kshiftlw.kshiftlb.kshiftlq.kshiftld.html'>KSHIFTLB</a></td><td>Shift Left Mask Registers</td></tr><tr><td><a href='kshiftlw.kshiftlb.kshiftlq.kshiftld.html'>KSHIFTLD</a></td><td>Shift Left Mask Registers</td></tr><tr><td><a href='kshiftlw.kshiftlb.kshiftlq.kshiftld.html'>KSHIFTLQ</a></td><td>Shift Left Mask Registers</td></tr><tr><td><a href='kshiftlw.kshiftlb.kshiftlq.kshiftld.html'>KSHIFTLW</a></td><td>Shift Left Mask Registers</td></tr><tr><td><a href='kshiftrw.kshiftrb.kshiftrq.kshiftrd.html'>KSHIFTRB</a></td><td>Shift Right Mask Registers</td></tr><tr><td><a href='kshiftrw.kshiftrb.kshiftrq.kshiftrd.html'>KSHIFTRD</a></td><td>Shift Right Mask Registers</td></tr><tr><td><a href='kshiftrw.kshiftrb.kshiftrq.kshiftrd.html'>KSHIFTRQ</a></td><td>Shift Right Mask Registers</td></tr><tr><td><a href='kshiftrw.kshiftrb.kshiftrq.kshiftrd.html'>KSHIFTRW</a></td><td>Shift Right Mask Registers</td></tr><tr><td><a href='ktestw.ktestb.ktestq.ktestd.html'>KTESTB</a></td><td>Packed Bit Test Masks and Set Flags</td></tr><tr><td><a href='ktestw.ktestb.ktestq.ktestd.html'>KTESTD</a></td><td>Packed Bit Test Masks and Set Flags</td></tr><tr><td><a href='ktestw.ktestb.ktestq.ktestd.html'>KTESTQ</a></td><td>Packed Bit Test Masks and Set Flags</td></tr><tr><td><a href='ktestw.ktestb.ktestq.ktestd.html'>KTESTW</a></td><td>Packed Bit Test Masks and Set Flags</td></tr><tr><td><a href='kunpckbw.kunpckwd.kunpckdq.html'>KUNPCKBW</a></td><td>Unpack for Mask Registers</td></tr><tr><td><a href='kunpckbw.kunpckwd.kunpckdq.html'>KUNPCKDQ</a></td><td>Unpack for Mask Registers</td></tr><tr><td><a href='kunpckbw.kunpckwd.kunpckdq.html'>KUNPCKWD</a></td><td>Unpack for Mask Registers</td></tr><tr><td><a href='kxnorw.kxnorb.kxnorq.kxnord.html'>KXNORB</a></td><td>Bitwise Logical XNOR Masks</td></tr><tr><td><a href='kxnorw.kxnorb.kxnorq.kxnord.html'>KXNORD</a></td><td>Bitwise Logical XNOR Masks</td></tr><tr><td><a href='kxnorw.kxnorb.kxnorq.kxnord.html'>KXNORQ</a></td><td>Bitwise Logical XNOR Masks</td></tr><tr><td><a href='kxnorw.kxnorb.kxnorq.kxnord.html'>KXNORW</a></td><td>Bitwise Logical XNOR Masks</td></tr><tr><td><a href='kxorw.kxorb.kxorq.kxord.html'>KXORB</a></td><td>Bitwise Logical XOR Masks</td></tr><tr><td><a href='kxorw.kxorb.kxorq.kxord.html'>KXORD</a></td><td>Bitwise Logical XOR Masks</td></tr><tr><td><a href='kxorw.kxorb.kxorq.kxord.html'>KXORQ</a></td><td>Bitwise Logical XOR Masks</td></tr><tr><td><a href='kxorw.kxorb.kxorq.kxord.html'>KXORW</a></td><td>Bitwise Logical XOR Masks</td></tr><tr><td><a href='lahf.html'>LAHF</a></td><td>Load Status Flags Into AH Register</td></tr><tr><td><a href='lar.html'>LAR</a></td><td>Load Access Rights Byte</td></tr><tr><td><a href='lddqu.html'>LDDQU</a></td><td>Load Unaligned Integer 128 Bits</td></tr><tr><td><a href='ldmxcsr.html'>LDMXCSR</a></td><td>Load MXCSR Register</td></tr><tr><td><a href='lds.les.lfs.lgs.lss.html'>LDS</a></td><td>Load Far Pointer</td></tr><tr><td><a href='ldtilecfg.html'>LDTILECFG</a></td><td>Load Tile Configuration</td></tr><tr><td><a href='lea.html'>LEA</a></td><td>Load Effective Address</td></tr><tr><td><a href='leave.html'>LEAVE</a></td><td>High Level Procedure Exit</td></tr><tr><td><a href='lds.les.lfs.lgs.lss.html'>LES</a></td><td>Load Far Pointer</td></tr><tr><td><a href='lfence.html'>LFENCE</a></td><td>Load Fence</td></tr><tr><td><a href='lds.les.lfs.lgs.lss.html'>LFS</a></td><td>Load Far Pointer</td></tr><tr><td><a href='lgdt.lidt.html'>LGDT</a></td><td>Load Global/Interrupt Descriptor Table Register</td></tr><tr><td><a href='lds.les.lfs.lgs.lss.html'>LGS</a></td><td>Load Far Pointer</td></tr><tr><td><a href='lgdt.lidt.html'>LIDT</a></td><td>Load Global/Interrupt Descriptor Table Register</td></tr><tr><td><a href='lldt.html'>LLDT</a></td><td>Load Local Descriptor Table Register</td></tr><tr><td><a href='lmsw.html'>LMSW</a></td><td>Load Machine Status Word</td></tr><tr><td><a href='loadiwkey.html'>LOADIWKEY</a></td><td>Load Internal Wrapping Key With Key Locker</td></tr><tr><td><a href='lock.html'>LOCK</a></td><td>Assert LOCK# Signal Prefix</td></tr><tr><td><a href='lods.lodsb.lodsw.lodsd.lodsq.html'>LODS</a></td><td>Load String</td></tr><tr><td><a href='lods.lodsb.lodsw.lodsd.lodsq.html'>LODSB</a></td><td>Load String</td></tr><tr><td><a href='lods.lodsb.lodsw.lodsd.lodsq.html'>LODSD</a></td><td>Load String</td></tr><tr><td><a href='lods.lodsb.lodsw.lodsd.lodsq.html'>LODSQ</a></td><td>Load String</td></tr><tr><td><a href='lods.lodsb.lodsw.lodsd.lodsq.html'>LODSW</a></td><td>Load String</td></tr><tr><td><a href='loop.loopcc.html'>LOOP</a></td><td>Loop According to ECX Counter</td></tr><tr><td><a href='loop.loopcc.html'>LOOPcc</a></td><td>Loop According to ECX Counter</td></tr><tr><td><a href='lsl.html'>LSL</a></td><td>Load Segment Limit</td></tr><tr><td><a href='lds.les.lfs.lgs.lss.html'>LSS</a></td><td>Load Far Pointer</td></tr><tr><td><a href='ltr.html'>LTR</a></td><td>Load Task Register</td></tr><tr><td><a href='lzcnt.html'>LZCNT</a></td><td>Count the Number of Leading Zero Bits</td></tr><tr><td><a href='maskmovdqu.html'>MASKMOVDQU</a></td><td>Store Selected Bytes of Double Quadword</td></tr><tr><td><a href='maskmovq.html'>MASKMOVQ</a></td><td>Store Selected Bytes of Quadword</td></tr><tr><td><a href='maxpd.html'>MAXPD</a></td><td>Maximum of Packed Double Precision Floating-Point Values</td></tr><tr><td><a href='maxps.html'>MAXPS</a></td><td>Maximum of Packed Single Precision Floating-Point Values</td></tr><tr><td><a href='maxsd.html'>MAXSD</a></td><td>Return Maximum Scalar Double Precision Floating-Point Value</td></tr><tr><td><a href='maxss.html'>MAXSS</a></td><td>Return Maximum Scalar Single Precision Floating-Point Value</td></tr><tr><td><a href='mfence.html'>MFENCE</a></td><td>Memory Fence</td></tr><tr><td><a href='minpd.html'>MINPD</a></td><td>Minimum of Packed Double Precision Floating-Point Values</td></tr><tr><td><a href='minps.html'>MINPS</a></td><td>Minimum of Packed Single Precision Floating-Point Values</td></tr><tr><td><a href='minsd.html'>MINSD</a></td><td>Return Minimum Scalar Double Precision Floating-Point Value</td></tr><tr><td><a href='minss.html'>MINSS</a></td><td>Return Minimum Scalar Single Precision Floating-Point Value</td></tr><tr><td><a href='monitor.html'>MONITOR</a></td><td>Set Up Monitor Address</td></tr><tr><td><a href='mov.html'>MOV</a></td><td>Move</td></tr><tr><td><a href='mov-1.html'>MOV</a> (1)</td><td>Move to/from Control Registers</td></tr><tr><td><a href='mov-2.html'>MOV</a> (2)</td><td>Move to/from Debug Registers</td></tr><tr><td><a href='movapd.html'>MOVAPD</a></td><td>Move Aligned Packed Double Precision Floating-Point Values</td></tr><tr><td><a href='movaps.html'>MOVAPS</a></td><td>Move Aligned Packed Single Precision Floating-Point Values</td></tr><tr><td><a href='movbe.html'>MOVBE</a></td><td>Move Data After Swapping Bytes</td></tr><tr><td><a href='movd.movq.html'>MOVD</a></td><td>Move Doubleword/Move Quadword</td></tr><tr><td><a href='movddup.html'>MOVDDUP</a></td><td>Replicate Double Precision Floating-Point Values</td></tr><tr><td><a href='movdir64b.html'>MOVDIR64B</a></td><td>Move 64 Bytes as Direct Store</td></tr><tr><td><a href='movdiri.html'>MOVDIRI</a></td><td>Move Doubleword as Direct Store</td></tr><tr><td><a href='movdq2q.html'>MOVDQ2Q</a></td><td>Move Quadword from XMM to MMX Technology Register</td></tr><tr><td><a href='movdqa.vmovdqa32.vmovdqa64.html'>MOVDQA</a></td><td>Move Aligned Packed Integer Values</td></tr><tr><td><a href='movdqu.vmovdqu8.vmovdqu16.vmovdqu32.vmovdqu64.html'>MOVDQU</a></td><td>Move Unaligned Packed Integer Values</td></tr><tr><td><a href='movhlps.html'>MOVHLPS</a></td><td>Move Packed Single Precision Floating-Point Values High to Low</td></tr><tr><td><a href='movhpd.html'>MOVHPD</a></td><td>Move High Packed Double Precision Floating-Point Value</td></tr><tr><td><a href='movhps.html'>MOVHPS</a></td><td>Move High Packed Single Precision Floating-Point Values</td></tr><tr><td><a href='movlhps.html'>MOVLHPS</a></td><td>Move Packed Single Precision Floating-Point Values Low to High</td></tr><tr><td><a href='movlpd.html'>MOVLPD</a></td><td>Move Low Packed Double Precision Floating-Point Value</td></tr><tr><td><a href='movlps.html'>MOVLPS</a></td><td>Move Low Packed Single Precision Floating-Point Values</td></tr><tr><td><a href='movmskpd.html'>MOVMSKPD</a></td><td>Extract Packed Double Precision Floating-Point Sign Mask</td></tr><tr><td><a href='movmskps.html'>MOVMSKPS</a></td><td>Extract Packed Single Precision Floating-Point Sign Mask</td></tr><tr><td><a href='movntdq.html'>MOVNTDQ</a></td><td>Store Packed Integers Using Non-Temporal Hint</td></tr><tr><td><a href='movntdqa.html'>MOVNTDQA</a></td><td>Load Double Quadword Non-Temporal Aligned Hint</td></tr><tr><td><a href='movnti.html'>MOVNTI</a></td><td>Store Doubleword Using Non-Temporal Hint</td></tr><tr><td><a href='movntpd.html'>MOVNTPD</a></td><td>Store Packed Double Precision Floating-Point Values Using Non-Temporal Hint</td></tr><tr><td><a href='movntps.html'>MOVNTPS</a></td><td>Store Packed Single Precision Floating-Point Values Using Non-Temporal Hint</td></tr><tr><td><a href='movntq.html'>MOVNTQ</a></td><td>Store of Quadword Using Non-Temporal Hint</td></tr><tr><td><a href='movd.movq.html'>MOVQ</a></td><td>Move Doubleword/Move Quadword</td></tr><tr><td><a href='movq.html'>MOVQ</a> (1)</td><td>Move Quadword</td></tr><tr><td><a href='movq2dq.html'>MOVQ2DQ</a></td><td>Move Quadword from MMX Technology to XMM Register</td></tr><tr><td><a href='movs.movsb.movsw.movsd.movsq.html'>MOVS</a></td><td>Move Data From String to String</td></tr><tr><td><a href='movs.movsb.movsw.movsd.movsq.html'>MOVSB</a></td><td>Move Data From String to String</td></tr><tr><td><a href='movs.movsb.movsw.movsd.movsq.html'>MOVSD</a></td><td>Move Data From String to String</td></tr><tr><td><a href='movsd.html'>MOVSD</a> (1)</td><td>Move or Merge Scalar Double Precision Floating-Point Value</td></tr><tr><td><a href='movshdup.html'>MOVSHDUP</a></td><td>Replicate Single Precision Floating-Point Values</td></tr><tr><td><a href='movsldup.html'>MOVSLDUP</a></td><td>Replicate Single Precision Floating-Point Values</td></tr><tr><td><a href='movs.movsb.movsw.movsd.movsq.html'>MOVSQ</a></td><td>Move Data From String to String</td></tr><tr><td><a href='movss.html'>MOVSS</a></td><td>Move or Merge Scalar Single Precision Floating-Point Value</td></tr><tr><td><a href='movs.movsb.movsw.movsd.movsq.html'>MOVSW</a></td><td>Move Data From String to String</td></tr><tr><td><a href='movsx.movsxd.html'>MOVSX</a></td><td>Move With Sign-Extension</td></tr><tr><td><a href='movsx.movsxd.html'>MOVSXD</a></td><td>Move With Sign-Extension</td></tr><tr><td><a href='movupd.html'>MOVUPD</a></td><td>Move Unaligned Packed Double Precision Floating-Point Values</td></tr><tr><td><a href='movups.html'>MOVUPS</a></td><td>Move Unaligned Packed Single Precision Floating-Point Values</td></tr><tr><td><a href='movzx.html'>MOVZX</a></td><td>Move With Zero-Extend</td></tr><tr><td><a href='mpsadbw.html'>MPSADBW</a></td><td>Compute Multiple Packed Sums of Absolute Difference</td></tr><tr><td><a href='mul.html'>MUL</a></td><td>Unsigned Multiply</td></tr><tr><td><a href='mulpd.html'>MULPD</a></td><td>Multiply Packed Double Precision Floating-Point Values</td></tr><tr><td><a href='mulps.html'>MULPS</a></td><td>Multiply Packed Single Precision Floating-Point Values</td></tr><tr><td><a href='mulsd.html'>MULSD</a></td><td>Multiply Scalar Double Precision Floating-Point Value</td></tr><tr><td><a href='mulss.html'>MULSS</a></td><td>Multiply Scalar Single Precision Floating-Point Values</td></tr><tr><td><a href='mulx.html'>MULX</a></td><td>Unsigned Multiply Without Affecting Flags</td></tr><tr><td><a href='mwait.html'>MWAIT</a></td><td>Monitor Wait</td></tr><tr><td><a href='neg.html'>NEG</a></td><td>Two's Complement Negation</td></tr><tr><td><a href='nop.html'>NOP</a></td><td>No Operation</td></tr><tr><td><a href='not.html'>NOT</a></td><td>One's Complement Negation</td></tr><tr><td><a href='or.html'>OR</a></td><td>Logical Inclusive OR</td></tr><tr><td><a href='orpd.html'>ORPD</a></td><td>Bitwise Logical OR of Packed Double Precision Floating-Point Values</td></tr><tr><td><a href='orps.html'>ORPS</a></td><td>Bitwise Logical OR of Packed Single Precision Floating-Point Values</td></tr><tr><td><a href='out.html'>OUT</a></td><td>Output to Port</td></tr><tr><td><a href='outs.outsb.outsw.outsd.html'>OUTS</a></td><td>Output String to Port</td></tr><tr><td><a href='outs.outsb.outsw.outsd.html'>OUTSB</a></td><td>Output String to Port</td></tr><tr><td><a href='outs.outsb.outsw.outsd.html'>OUTSD</a></td><td>Output String to Port</td></tr><tr><td><a href='outs.outsb.outsw.outsd.html'>OUTSW</a></td><td>Output String to Port</td></tr><tr><td><a href='pabsb.pabsw.pabsd.pabsq.html'>PABSB</a></td><td>Packed Absolute Value</td></tr><tr><td><a href='pabsb.pabsw.pabsd.pabsq.html'>PABSD</a></td><td>Packed Absolute Value</td></tr><tr><td><a href='pabsb.pabsw.pabsd.pabsq.html'>PABSQ</a></td><td>Packed Absolute Value</td></tr><tr><td><a href='pabsb.pabsw.pabsd.pabsq.html'>PABSW</a></td><td>Packed Absolute Value</td></tr><tr><td><a href='packsswb.packssdw.html'>PACKSSDW</a></td><td>Pack With Signed Saturation</td></tr><tr><td><a href='packsswb.packssdw.html'>PACKSSWB</a></td><td>Pack With Signed Saturation</td></tr><tr><td><a href='packusdw.html'>PACKUSDW</a></td><td>Pack With Unsigned Saturation</td></tr><tr><td><a href='packuswb.html'>PACKUSWB</a></td><td>Pack With Unsigned Saturation</td></tr><tr><td><a href='paddb.paddw.paddd.paddq.html'>PADDB</a></td><td>Add Packed Integers</td></tr><tr><td><a href='paddb.paddw.paddd.paddq.html'>PADDD</a></td><td>Add Packed Integers</td></tr><tr><td><a href='paddb.paddw.paddd.paddq.html'>PADDQ</a></td><td>Add Packed Integers</td></tr><tr><td><a href='paddsb.paddsw.html'>PADDSB</a></td><td>Add Packed Signed Integers with Signed Saturation</td></tr><tr><td><a href='paddsb.paddsw.html'>PADDSW</a></td><td>Add Packed Signed Integers with Signed Saturation</td></tr><tr><td><a href='paddusb.paddusw.html'>PADDUSB</a></td><td>Add Packed Unsigned Integers With Unsigned Saturation</td></tr><tr><td><a href='paddusb.paddusw.html'>PADDUSW</a></td><td>Add Packed Unsigned Integers With Unsigned Saturation</td></tr><tr><td><a href='paddb.paddw.paddd.paddq.html'>PADDW</a></td><td>Add Packed Integers</td></tr><tr><td><a href='palignr.html'>PALIGNR</a></td><td>Packed Align Right</td></tr><tr><td><a href='pand.html'>PAND</a></td><td>Logical AND</td></tr><tr><td><a href='pandn.html'>PANDN</a></td><td>Logical AND NOT</td></tr><tr><td><a href='pause.html'>PAUSE</a></td><td>Spin Loop Hint</td></tr><tr><td><a href='pavgb.pavgw.html'>PAVGB</a></td><td>Average Packed Integers</td></tr><tr><td><a href='pavgb.pavgw.html'>PAVGW</a></td><td>Average Packed Integers</td></tr><tr><td><a href='pblendvb.html'>PBLENDVB</a></td><td>Variable Blend Packed Bytes</td></tr><tr><td><a href='pblendw.html'>PBLENDW</a></td><td>Blend Packed Words</td></tr><tr><td><a href='pclmulqdq.html'>PCLMULQDQ</a></td><td>Carry-Less Multiplication Quadword</td></tr><tr><td><a href='pcmpeqb.pcmpeqw.pcmpeqd.html'>PCMPEQB</a></td><td>Compare Packed Data for Equal</td></tr><tr><td><a href='pcmpeqb.pcmpeqw.pcmpeqd.html'>PCMPEQD</a></td><td>Compare Packed Data for Equal</td></tr><tr><td><a href='pcmpeqq.html'>PCMPEQQ</a></td><td>Compare Packed Qword Data for Equal</td></tr><tr><td><a href='pcmpeqb.pcmpeqw.pcmpeqd.html'>PCMPEQW</a></td><td>Compare Packed Data for Equal</td></tr><tr><td><a href='pcmpestri.html'>PCMPESTRI</a></td><td>Packed Compare Explicit Length Strings, Return Index</td></tr><tr><td><a href='pcmpestrm.html'>PCMPESTRM</a></td><td>Packed Compare Explicit Length Strings, Return Mask</td></tr><tr><td><a href='pcmpgtb.pcmpgtw.pcmpgtd.html'>PCMPGTB</a></td><td>Compare Packed Signed Integers for Greater Than</td></tr><tr><td><a href='pcmpgtb.pcmpgtw.pcmpgtd.html'>PCMPGTD</a></td><td>Compare Packed Signed Integers for Greater Than</td></tr><tr><td><a href='pcmpgtq.html'>PCMPGTQ</a></td><td>Compare Packed Data for Greater Than</td></tr><tr><td><a href='pcmpgtb.pcmpgtw.pcmpgtd.html'>PCMPGTW</a></td><td>Compare Packed Signed Integers for Greater Than</td></tr><tr><td><a href='pcmpistri.html'>PCMPISTRI</a></td><td>Packed Compare Implicit Length Strings, Return Index</td></tr><tr><td><a href='pcmpistrm.html'>PCMPISTRM</a></td><td>Packed Compare Implicit Length Strings, Return Mask</td></tr><tr><td><a href='pconfig.html'>PCONFIG</a></td><td>Platform Configuration</td></tr><tr><td><a href='pdep.html'>PDEP</a></td><td>Parallel Bits Deposit</td></tr><tr><td><a href='pext.html'>PEXT</a></td><td>Parallel Bits Extract</td></tr><tr><td><a href='pextrb.pextrd.pextrq.html'>PEXTRB</a></td><td>Extract Byte/Dword/Qword</td></tr><tr><td><a href='pextrb.pextrd.pextrq.html'>PEXTRD</a></td><td>Extract Byte/Dword/Qword</td></tr><tr><td><a href='pextrb.pextrd.pextrq.html'>PEXTRQ</a></td><td>Extract Byte/Dword/Qword</td></tr><tr><td><a href='pextrw.html'>PEXTRW</a></td><td>Extract Word</td></tr><tr><td><a href='phaddw.phaddd.html'>PHADDD</a></td><td>Packed Horizontal Add</td></tr><tr><td><a href='phaddsw.html'>PHADDSW</a></td><td>Packed Horizontal Add and Saturate</td></tr><tr><td><a href='phaddw.phaddd.html'>PHADDW</a></td><td>Packed Horizontal Add</td></tr><tr><td><a href='phminposuw.html'>PHMINPOSUW</a></td><td>Packed Horizontal Word Minimum</td></tr><tr><td><a href='phsubw.phsubd.html'>PHSUBD</a></td><td>Packed Horizontal Subtract</td></tr><tr><td><a href='phsubsw.html'>PHSUBSW</a></td><td>Packed Horizontal Subtract and Saturate</td></tr><tr><td><a href='phsubw.phsubd.html'>PHSUBW</a></td><td>Packed Horizontal Subtract</td></tr><tr><td><a href='pinsrb.pinsrd.pinsrq.html'>PINSRB</a></td><td>Insert Byte/Dword/Qword</td></tr><tr><td><a href='pinsrb.pinsrd.pinsrq.html'>PINSRD</a></td><td>Insert Byte/Dword/Qword</td></tr><tr><td><a href='pinsrb.pinsrd.pinsrq.html'>PINSRQ</a></td><td>Insert Byte/Dword/Qword</td></tr><tr><td><a href='pinsrw.html'>PINSRW</a></td><td>Insert Word</td></tr><tr><td><a href='pmaddubsw.html'>PMADDUBSW</a></td><td>Multiply and Add Packed Signed and Unsigned Bytes</td></tr><tr><td><a href='pmaddwd.html'>PMADDWD</a></td><td>Multiply and Add Packed Integers</td></tr><tr><td><a href='pmaxsb.pmaxsw.pmaxsd.pmaxsq.html'>PMAXSB</a></td><td>Maximum of Packed Signed Integers</td></tr><tr><td><a href='pmaxsb.pmaxsw.pmaxsd.pmaxsq.html'>PMAXSD</a></td><td>Maximum of Packed Signed Integers</td></tr><tr><td><a href='pmaxsb.pmaxsw.pmaxsd.pmaxsq.html'>PMAXSQ</a></td><td>Maximum of Packed Signed Integers</td></tr><tr><td><a href='pmaxsb.pmaxsw.pmaxsd.pmaxsq.html'>PMAXSW</a></td><td>Maximum of Packed Signed Integers</td></tr><tr><td><a href='pmaxub.pmaxuw.html'>PMAXUB</a></td><td>Maximum of Packed Unsigned Integers</td></tr><tr><td><a href='pmaxud.pmaxuq.html'>PMAXUD</a></td><td>Maximum of Packed Unsigned Integers</td></tr><tr><td><a href='pmaxud.pmaxuq.html'>PMAXUQ</a></td><td>Maximum of Packed Unsigned Integers</td></tr><tr><td><a href='pmaxub.pmaxuw.html'>PMAXUW</a></td><td>Maximum of Packed Unsigned Integers</td></tr><tr><td><a href='pminsb.pminsw.html'>PMINSB</a></td><td>Minimum of Packed Signed Integers</td></tr><tr><td><a href='pminsd.pminsq.html'>PMINSD</a></td><td>Minimum of Packed Signed Integers</td></tr><tr><td><a href='pminsd.pminsq.html'>PMINSQ</a></td><td>Minimum of Packed Signed Integers</td></tr><tr><td><a href='pminsb.pminsw.html'>PMINSW</a></td><td>Minimum of Packed Signed Integers</td></tr><tr><td><a href='pminub.pminuw.html'>PMINUB</a></td><td>Minimum of Packed Unsigned Integers</td></tr><tr><td><a href='pminud.pminuq.html'>PMINUD</a></td><td>Minimum of Packed Unsigned Integers</td></tr><tr><td><a href='pminud.pminuq.html'>PMINUQ</a></td><td>Minimum of Packed Unsigned Integers</td></tr><tr><td><a href='pminub.pminuw.html'>PMINUW</a></td><td>Minimum of Packed Unsigned Integers</td></tr><tr><td><a href='pmovmskb.html'>PMOVMSKB</a></td><td>Move Byte Mask</td></tr><tr><td><a href='pmovsx.html'>PMOVSX</a></td><td>Packed Move With Sign Extend</td></tr><tr><td><a href='pmovzx.html'>PMOVZX</a></td><td>Packed Move With Zero Extend</td></tr><tr><td><a href='pmuldq.html'>PMULDQ</a></td><td>Multiply Packed Doubleword Integers</td></tr><tr><td><a href='pmulhrsw.html'>PMULHRSW</a></td><td>Packed Multiply High With Round and Scale</td></tr><tr><td><a href='pmulhuw.html'>PMULHUW</a></td><td>Multiply Packed Unsigned Integers and Store High Result</td></tr><tr><td><a href='pmulhw.html'>PMULHW</a></td><td>Multiply Packed Signed Integers and Store High Result</td></tr><tr><td><a href='pmulld.pmullq.html'>PMULLD</a></td><td>Multiply Packed Integers and Store Low Result</td></tr><tr><td><a href='pmulld.pmullq.html'>PMULLQ</a></td><td>Multiply Packed Integers and Store Low Result</td></tr><tr><td><a href='pmullw.html'>PMULLW</a></td><td>Multiply Packed Signed Integers and Store Low Result</td></tr><tr><td><a href='pmuludq.html'>PMULUDQ</a></td><td>Multiply Packed Unsigned Doubleword Integers</td></tr><tr><td><a href='pop.html'>POP</a></td><td>Pop a Value From the Stack</td></tr><tr><td><a href='popa.popad.html'>POPA</a></td><td>Pop All General-Purpose Registers</td></tr><tr><td><a href='popa.popad.html'>POPAD</a></td><td>Pop All General-Purpose Registers</td></tr><tr><td><a href='popcnt.html'>POPCNT</a></td><td>Return the Count of Number of Bits Set to 1</td></tr><tr><td><a href='popf.popfd.popfq.html'>POPF</a></td><td>Pop Stack Into EFLAGS Register</td></tr><tr><td><a href='popf.popfd.popfq.html'>POPFD</a></td><td>Pop Stack Into EFLAGS Register</td></tr><tr><td><a href='popf.popfd.popfq.html'>POPFQ</a></td><td>Pop Stack Into EFLAGS Register</td></tr><tr><td><a href='por.html'>POR</a></td><td>Bitwise Logical OR</td></tr><tr><td><a href='prefetchw.html'>PREFETCHW</a></td><td>Prefetch Data Into Caches in Anticipation of a Write</td></tr><tr><td><a href='prefetchh.html'>PREFETCHh</a></td><td>Prefetch Data Into Caches</td></tr><tr><td><a href='psadbw.html'>PSADBW</a></td><td>Compute Sum of Absolute Differences</td></tr><tr><td><a href='pshufb.html'>PSHUFB</a></td><td>Packed Shuffle Bytes</td></tr><tr><td><a href='pshufd.html'>PSHUFD</a></td><td>Shuffle Packed Doublewords</td></tr><tr><td><a href='pshufhw.html'>PSHUFHW</a></td><td>Shuffle Packed High Words</td></tr><tr><td><a href='pshuflw.html'>PSHUFLW</a></td><td>Shuffle Packed Low Words</td></tr><tr><td><a href='pshufw.html'>PSHUFW</a></td><td>Shuffle Packed Words</td></tr><tr><td><a href='psignb.psignw.psignd.html'>PSIGNB</a></td><td>Packed SIGN</td></tr><tr><td><a href='psignb.psignw.psignd.html'>PSIGND</a></td><td>Packed SIGN</td></tr><tr><td><a href='psignb.psignw.psignd.html'>PSIGNW</a></td><td>Packed SIGN</td></tr><tr><td><a href='psllw.pslld.psllq.html'>PSLLD</a></td><td>Shift Packed Data Left Logical</td></tr><tr><td><a href='pslldq.html'>PSLLDQ</a></td><td>Shift Double Quadword Left Logical</td></tr><tr><td><a href='psllw.pslld.psllq.html'>PSLLQ</a></td><td>Shift Packed Data Left Logical</td></tr><tr><td><a href='psllw.pslld.psllq.html'>PSLLW</a></td><td>Shift Packed Data Left Logical</td></tr><tr><td><a href='psraw.psrad.psraq.html'>PSRAD</a></td><td>Shift Packed Data Right Arithmetic</td></tr><tr><td><a href='psraw.psrad.psraq.html'>PSRAQ</a></td><td>Shift Packed Data Right Arithmetic</td></tr><tr><td><a href='psraw.psrad.psraq.html'>PSRAW</a></td><td>Shift Packed Data Right Arithmetic</td></tr><tr><td><a href='psrlw.psrld.psrlq.html'>PSRLD</a></td><td>Shift Packed Data Right Logical</td></tr><tr><td><a href='psrldq.html'>PSRLDQ</a></td><td>Shift Double Quadword Right Logical</td></tr><tr><td><a href='psrlw.psrld.psrlq.html'>PSRLQ</a></td><td>Shift Packed Data Right Logical</td></tr><tr><td><a href='psrlw.psrld.psrlq.html'>PSRLW</a></td><td>Shift Packed Data Right Logical</td></tr><tr><td><a href='psubb.psubw.psubd.html'>PSUBB</a></td><td>Subtract Packed Integers</td></tr><tr><td><a href='psubb.psubw.psubd.html'>PSUBD</a></td><td>Subtract Packed Integers</td></tr><tr><td><a href='psubq.html'>PSUBQ</a></td><td>Subtract Packed Quadword Integers</td></tr><tr><td><a href='psubsb.psubsw.html'>PSUBSB</a></td><td>Subtract Packed Signed Integers With Signed Saturation</td></tr><tr><td><a href='psubsb.psubsw.html'>PSUBSW</a></td><td>Subtract Packed Signed Integers With Signed Saturation</td></tr><tr><td><a href='psubusb.psubusw.html'>PSUBUSB</a></td><td>Subtract Packed Unsigned Integers With Unsigned Saturation</td></tr><tr><td><a href='psubusb.psubusw.html'>PSUBUSW</a></td><td>Subtract Packed Unsigned Integers With Unsigned Saturation</td></tr><tr><td><a href='psubb.psubw.psubd.html'>PSUBW</a></td><td>Subtract Packed Integers</td></tr><tr><td><a href='ptest.html'>PTEST</a></td><td>Logical Compare</td></tr><tr><td><a href='ptwrite.html'>PTWRITE</a></td><td>Write Data to a Processor Trace Packet</td></tr><tr><td><a href='punpckhbw.punpckhwd.punpckhdq.punpckhqdq.html'>PUNPCKHBW</a></td><td>Unpack High Data</td></tr><tr><td><a href='punpckhbw.punpckhwd.punpckhdq.punpckhqdq.html'>PUNPCKHDQ</a></td><td>Unpack High Data</td></tr><tr><td><a href='punpckhbw.punpckhwd.punpckhdq.punpckhqdq.html'>PUNPCKHQDQ</a></td><td>Unpack High Data</td></tr><tr><td><a href='punpckhbw.punpckhwd.punpckhdq.punpckhqdq.html'>PUNPCKHWD</a></td><td>Unpack High Data</td></tr><tr><td><a href='punpcklbw.punpcklwd.punpckldq.punpcklqdq.html'>PUNPCKLBW</a></td><td>Unpack Low Data</td></tr><tr><td><a href='punpcklbw.punpcklwd.punpckldq.punpcklqdq.html'>PUNPCKLDQ</a></td><td>Unpack Low Data</td></tr><tr><td><a href='punpcklbw.punpcklwd.punpckldq.punpcklqdq.html'>PUNPCKLQDQ</a></td><td>Unpack Low Data</td></tr><tr><td><a href='punpcklbw.punpcklwd.punpckldq.punpcklqdq.html'>PUNPCKLWD</a></td><td>Unpack Low Data</td></tr><tr><td><a href='push.html'>PUSH</a></td><td>Push Word, Doubleword, or Quadword Onto the Stack</td></tr><tr><td><a href='pusha.pushad.html'>PUSHA</a></td><td>Push All General-Purpose Registers</td></tr><tr><td><a href='pusha.pushad.html'>PUSHAD</a></td><td>Push All General-Purpose Registers</td></tr><tr><td><a href='pushf.pushfd.pushfq.html'>PUSHF</a></td><td>Push EFLAGS Register Onto the Stack</td></tr><tr><td><a href='pushf.pushfd.pushfq.html'>PUSHFD</a></td><td>Push EFLAGS Register Onto the Stack</td></tr><tr><td><a href='pushf.pushfd.pushfq.html'>PUSHFQ</a></td><td>Push EFLAGS Register Onto the Stack</td></tr><tr><td><a href='pxor.html'>PXOR</a></td><td>Logical Exclusive OR</td></tr><tr><td><a href='rcl.rcr.rol.ror.html'>RCL</a></td><td>Rotate</td></tr><tr><td><a href='rcpps.html'>RCPPS</a></td><td>Compute Reciprocals of Packed Single Precision Floating-Point Values</td></tr><tr><td><a href='rcpss.html'>RCPSS</a></td><td>Compute Reciprocal of Scalar Single Precision Floating-Point Values</td></tr><tr><td><a href='rcl.rcr.rol.ror.html'>RCR</a></td><td>Rotate</td></tr><tr><td><a href='rdfsbase.rdgsbase.html'>RDFSBASE</a></td><td>Read FS/GS Segment Base</td></tr><tr><td><a href='rdfsbase.rdgsbase.html'>RDGSBASE</a></td><td>Read FS/GS Segment Base</td></tr><tr><td><a href='rdmsr.html'>RDMSR</a></td><td>Read From Model Specific Register</td></tr><tr><td><a href='rdpid.html'>RDPID</a></td><td>Read Processor ID</td></tr><tr><td><a href='rdpkru.html'>RDPKRU</a></td><td>Read Protection Key Rights for User Pages</td></tr><tr><td><a href='rdpmc.html'>RDPMC</a></td><td>Read Performance-Monitoring Counters</td></tr><tr><td><a href='rdrand.html'>RDRAND</a></td><td>Read Random Number</td></tr><tr><td><a href='rdseed.html'>RDSEED</a></td><td>Read Random SEED</td></tr><tr><td><a href='rdsspd.rdsspq.html'>RDSSPD</a></td><td>Read Shadow Stack Pointer</td></tr><tr><td><a href='rdsspd.rdsspq.html'>RDSSPQ</a></td><td>Read Shadow Stack Pointer</td></tr><tr><td><a href='rdtsc.html'>RDTSC</a></td><td>Read Time-Stamp Counter</td></tr><tr><td><a href='rdtscp.html'>RDTSCP</a></td><td>Read Time-Stamp Counter and Processor ID</td></tr><tr><td><a href='rep.repe.repz.repne.repnz.html'>REP</a></td><td>Repeat String Operation Prefix</td></tr><tr><td><a href='rep.repe.repz.repne.repnz.html'>REPE</a></td><td>Repeat String Operation Prefix</td></tr><tr><td><a href='rep.repe.repz.repne.repnz.html'>REPNE</a></td><td>Repeat String Operation Prefix</td></tr><tr><td><a href='rep.repe.repz.repne.repnz.html'>REPNZ</a></td><td>Repeat String Operation Prefix</td></tr><tr><td><a href='rep.repe.repz.repne.repnz.html'>REPZ</a></td><td>Repeat String Operation Prefix</td></tr><tr><td><a href='ret.html'>RET</a></td><td>Return From Procedure</td></tr><tr><td><a href='rcl.rcr.rol.ror.html'>ROL</a></td><td>Rotate</td></tr><tr><td><a href='rcl.rcr.rol.ror.html'>ROR</a></td><td>Rotate</td></tr><tr><td><a href='rorx.html'>RORX</a></td><td>Rotate Right Logical Without Affecting Flags</td></tr><tr><td><a href='roundpd.html'>ROUNDPD</a></td><td>Round Packed Double Precision Floating-Point Values</td></tr><tr><td><a href='roundps.html'>ROUNDPS</a></td><td>Round Packed Single Precision Floating-Point Values</td></tr><tr><td><a href='roundsd.html'>ROUNDSD</a></td><td>Round Scalar Double Precision Floating-Point Values</td></tr><tr><td><a href='roundss.html'>ROUNDSS</a></td><td>Round Scalar Single Precision Floating-Point Values</td></tr><tr><td><a href='rsm.html'>RSM</a></td><td>Resume From System Management Mode</td></tr><tr><td><a href='rsqrtps.html'>RSQRTPS</a></td><td>Compute Reciprocals of Square Roots of Packed Single Precision Floating-PointValues</td></tr><tr><td><a href='rsqrtss.html'>RSQRTSS</a></td><td>Compute Reciprocal of Square Root of Scalar Single Precision Floating-Point Value</td></tr><tr><td><a href='rstorssp.html'>RSTORSSP</a></td><td>Restore Saved Shadow Stack Pointer</td></tr><tr><td><a href='sahf.html'>SAHF</a></td><td>Store AH Into Flags</td></tr><tr><td><a href='sal.sar.shl.shr.html'>SAL</a></td><td>Shift</td></tr><tr><td><a href='sal.sar.shl.shr.html'>SAR</a></td><td>Shift</td></tr><tr><td><a href='sarx.shlx.shrx.html'>SARX</a></td><td>Shift Without Affecting Flags</td></tr><tr><td><a href='saveprevssp.html'>SAVEPREVSSP</a></td><td>Save Previous Shadow Stack Pointer</td></tr><tr><td><a href='sbb.html'>SBB</a></td><td>Integer Subtraction With Borrow</td></tr><tr><td><a href='scas.scasb.scasw.scasd.html'>SCAS</a></td><td>Scan String</td></tr><tr><td><a href='scas.scasb.scasw.scasd.html'>SCASB</a></td><td>Scan String</td></tr><tr><td><a href='scas.scasb.scasw.scasd.html'>SCASD</a></td><td>Scan String</td></tr><tr><td><a href='scas.scasb.scasw.scasd.html'>SCASW</a></td><td>Scan String</td></tr><tr><td><a href='senduipi.html'>SENDUIPI</a></td><td>Send User Interprocessor Interrupt</td></tr><tr><td><a href='serialize.html'>SERIALIZE</a></td><td>Serialize Instruction Execution</td></tr><tr><td><a href='setssbsy.html'>SETSSBSY</a></td><td>Mark Shadow Stack Busy</td></tr><tr><td><a href='setcc.html'>SETcc</a></td><td>Set Byte on Condition</td></tr><tr><td><a href='sfence.html'>SFENCE</a></td><td>Store Fence</td></tr><tr><td><a href='sgdt.html'>SGDT</a></td><td>Store Global Descriptor Table Register</td></tr><tr><td><a href='sha1msg1.html'>SHA1MSG1</a></td><td>Perform an Intermediate Calculation for the Next Four SHA1 Message Dwords</td></tr><tr><td><a href='sha1msg2.html'>SHA1MSG2</a></td><td>Perform a Final Calculation for the Next Four SHA1 Message Dwords</td></tr><tr><td><a href='sha1nexte.html'>SHA1NEXTE</a></td><td>Calculate SHA1 State Variable E After Four Rounds</td></tr><tr><td><a href='sha1rnds4.html'>SHA1RNDS4</a></td><td>Perform Four Rounds of SHA1 Operation</td></tr><tr><td><a href='sha256msg1.html'>SHA256MSG1</a></td><td>Perform an Intermediate Calculation for the Next Four SHA256 MessageDwords</td></tr><tr><td><a href='sha256msg2.html'>SHA256MSG2</a></td><td>Perform a Final Calculation for the Next Four SHA256 Message Dwords</td></tr><tr><td><a href='sha256rnds2.html'>SHA256RNDS2</a></td><td>Perform Two Rounds of SHA256 Operation</td></tr><tr><td><a href='sal.sar.shl.shr.html'>SHL</a></td><td>Shift</td></tr><tr><td><a href='shld.html'>SHLD</a></td><td>Double Precision Shift Left</td></tr><tr><td><a href='sarx.shlx.shrx.html'>SHLX</a></td><td>Shift Without Affecting Flags</td></tr><tr><td><a href='sal.sar.shl.shr.html'>SHR</a></td><td>Shift</td></tr><tr><td><a href='shrd.html'>SHRD</a></td><td>Double Precision Shift Right</td></tr><tr><td><a href='sarx.shlx.shrx.html'>SHRX</a></td><td>Shift Without Affecting Flags</td></tr><tr><td><a href='shufpd.html'>SHUFPD</a></td><td>Packed Interleave Shuffle of Pairs of Double Precision Floating-Point Values</td></tr><tr><td><a href='shufps.html'>SHUFPS</a></td><td>Packed Interleave Shuffle of Quadruplets of Single Precision Floating-Point Values</td></tr><tr><td><a href='sidt.html'>SIDT</a></td><td>Store Interrupt Descriptor Table Register</td></tr><tr><td><a href='sldt.html'>SLDT</a></td><td>Store Local Descriptor Table Register</td></tr><tr><td><a href='smsw.html'>SMSW</a></td><td>Store Machine Status Word</td></tr><tr><td><a href='sqrtpd.html'>SQRTPD</a></td><td>Square Root of Double Precision Floating-Point Values</td></tr><tr><td><a href='sqrtps.html'>SQRTPS</a></td><td>Square Root of Single Precision Floating-Point Values</td></tr><tr><td><a href='sqrtsd.html'>SQRTSD</a></td><td>Compute Square Root of Scalar Double Precision Floating-Point Value</td></tr><tr><td><a href='sqrtss.html'>SQRTSS</a></td><td>Compute Square Root of Scalar Single Precision Value</td></tr><tr><td><a href='stac.html'>STAC</a></td><td>Set AC Flag in EFLAGS Register</td></tr><tr><td><a href='stc.html'>STC</a></td><td>Set Carry Flag</td></tr><tr><td><a href='std.html'>STD</a></td><td>Set Direction Flag</td></tr><tr><td><a href='sti.html'>STI</a></td><td>Set Interrupt Flag</td></tr><tr><td><a href='stmxcsr.html'>STMXCSR</a></td><td>Store MXCSR Register State</td></tr><tr><td><a href='stos.stosb.stosw.stosd.stosq.html'>STOS</a></td><td>Store String</td></tr><tr><td><a href='stos.stosb.stosw.stosd.stosq.html'>STOSB</a></td><td>Store String</td></tr><tr><td><a href='stos.stosb.stosw.stosd.stosq.html'>STOSD</a></td><td>Store String</td></tr><tr><td><a href='stos.stosb.stosw.stosd.stosq.html'>STOSQ</a></td><td>Store String</td></tr><tr><td><a href='stos.stosb.stosw.stosd.stosq.html'>STOSW</a></td><td>Store String</td></tr><tr><td><a href='str.html'>STR</a></td><td>Store Task Register</td></tr><tr><td><a href='sttilecfg.html'>STTILECFG</a></td><td>Store Tile Configuration</td></tr><tr><td><a href='stui.html'>STUI</a></td><td>Set User Interrupt Flag</td></tr><tr><td><a href='sub.html'>SUB</a></td><td>Subtract</td></tr><tr><td><a href='subpd.html'>SUBPD</a></td><td>Subtract Packed Double Precision Floating-Point Values</td></tr><tr><td><a href='subps.html'>SUBPS</a></td><td>Subtract Packed Single Precision Floating-Point Values</td></tr><tr><td><a href='subsd.html'>SUBSD</a></td><td>Subtract Scalar Double Precision Floating-Point Value</td></tr><tr><td><a href='subss.html'>SUBSS</a></td><td>Subtract Scalar Single Precision Floating-Point Value</td></tr><tr><td><a href='swapgs.html'>SWAPGS</a></td><td>Swap GS Base Register</td></tr><tr><td><a href='syscall.html'>SYSCALL</a></td><td>Fast System Call</td></tr><tr><td><a href='sysenter.html'>SYSENTER</a></td><td>Fast System Call</td></tr><tr><td><a href='sysexit.html'>SYSEXIT</a></td><td>Fast Return from Fast System Call</td></tr><tr><td><a href='sysret.html'>SYSRET</a></td><td>Return From Fast System Call</td></tr><tr><td><a href='tdpbf16ps.html'>TDPBF16PS</a></td><td>Dot Product of BF16 Tiles Accumulated into Packed Single Precision Tile</td></tr><tr><td><a href='tdpbssd.tdpbsud.tdpbusd.tdpbuud.html'>TDPBSSD</a></td><td>Dot Product of Signed/Unsigned Bytes with DwordAccumulation</td></tr><tr><td><a href='tdpbssd.tdpbsud.tdpbusd.tdpbuud.html'>TDPBSUD</a></td><td>Dot Product of Signed/Unsigned Bytes with DwordAccumulation</td></tr><tr><td><a href='tdpbssd.tdpbsud.tdpbusd.tdpbuud.html'>TDPBUSD</a></td><td>Dot Product of Signed/Unsigned Bytes with DwordAccumulation</td></tr><tr><td><a href='tdpbssd.tdpbsud.tdpbusd.tdpbuud.html'>TDPBUUD</a></td><td>Dot Product of Signed/Unsigned Bytes with DwordAccumulation</td></tr><tr><td><a href='test.html'>TEST</a></td><td>Logical Compare</td></tr><tr><td><a href='testui.html'>TESTUI</a></td><td>Determine User Interrupt Flag</td></tr><tr><td><a href='tileloadd.tileloaddt1.html'>TILELOADD</a></td><td>Load Tile</td></tr><tr><td><a href='tileloadd.tileloaddt1.html'>TILELOADDT1</a></td><td>Load Tile</td></tr><tr><td><a href='tilerelease.html'>TILERELEASE</a></td><td>Release Tile</td></tr><tr><td><a href='tilestored.html'>TILESTORED</a></td><td>Store Tile</td></tr><tr><td><a href='tilezero.html'>TILEZERO</a></td><td>Zero Tile</td></tr><tr><td><a href='tpause.html'>TPAUSE</a></td><td>Timed PAUSE</td></tr><tr><td><a href='tzcnt.html'>TZCNT</a></td><td>Count the Number of Trailing Zero Bits</td></tr><tr><td><a href='ucomisd.html'>UCOMISD</a></td><td>Unordered Compare Scalar Double Precision Floating-Point Values and Set EFLAGS</td></tr><tr><td><a href='ucomiss.html'>UCOMISS</a></td><td>Unordered Compare Scalar Single Precision Floating-Point Values and Set EFLAGS</td></tr><tr><td><a href='ud.html'>UD</a></td><td>Undefined Instruction</td></tr><tr><td><a href='uiret.html'>UIRET</a></td><td>User-Interrupt Return</td></tr><tr><td><a href='umonitor.html'>UMONITOR</a></td><td>User Level Set Up Monitor Address</td></tr><tr><td><a href='umwait.html'>UMWAIT</a></td><td>User Level Monitor Wait</td></tr><tr><td><a href='unpckhpd.html'>UNPCKHPD</a></td><td>Unpack and Interleave High Packed Double Precision Floating-Point Values</td></tr><tr><td><a href='unpckhps.html'>UNPCKHPS</a></td><td>Unpack and Interleave High Packed Single Precision Floating-Point Values</td></tr><tr><td><a href='unpcklpd.html'>UNPCKLPD</a></td><td>Unpack and Interleave Low Packed Double Precision Floating-Point Values</td></tr><tr><td><a href='unpcklps.html'>UNPCKLPS</a></td><td>Unpack and Interleave Low Packed Single Precision Floating-Point Values</td></tr><tr><td><a href='vaddph.html'>VADDPH</a></td><td>Add Packed FP16 Values</td></tr><tr><td><a href='vaddsh.html'>VADDSH</a></td><td>Add Scalar FP16 Values</td></tr><tr><td><a href='valignd.valignq.html'>VALIGND</a></td><td>Align Doubleword/Quadword Vectors</td></tr><tr><td><a href='valignd.valignq.html'>VALIGNQ</a></td><td>Align Doubleword/Quadword Vectors</td></tr><tr><td><a href='vblendmpd.vblendmps.html'>VBLENDMPD</a></td><td>Blend Float64/Float32 Vectors Using an OpMask Control</td></tr><tr><td><a href='vblendmpd.vblendmps.html'>VBLENDMPS</a></td><td>Blend Float64/Float32 Vectors Using an OpMask Control</td></tr><tr><td><a href='vbroadcast.html'>VBROADCAST</a></td><td>Load with Broadcast Floating-Point Data</td></tr><tr><td><a href='vcmpph.html'>VCMPPH</a></td><td>Compare Packed FP16 Values</td></tr><tr><td><a href='vcmpsh.html'>VCMPSH</a></td><td>Compare Scalar FP16 Values</td></tr><tr><td><a href='vcomish.html'>VCOMISH</a></td><td>Compare Scalar Ordered FP16 Values and Set EFLAGS</td></tr><tr><td><a href='vcompresspd.html'>VCOMPRESSPD</a></td><td>Store Sparse Packed Double Precision Floating-Point Values Into DenseMemory</td></tr><tr><td><a href='vcompressps.html'>VCOMPRESSPS</a></td><td>Store Sparse Packed Single Precision Floating-Point Values Into Dense Memory</td></tr><tr><td><a href='vpcompressb.vcompressw.html'>VCOMPRESSW</a></td><td>Store Sparse Packed Byte/Word Integer Values Into DenseMemory/Register</td></tr><tr><td><a href='vcvtdq2ph.html'>VCVTDQ2PH</a></td><td>Convert Packed Signed Doubleword Integers to Packed FP16 Values</td></tr><tr><td><a href='vcvtne2ps2bf16.html'>VCVTNE2PS2BF16</a></td><td>Convert Two Packed Single Data to One Packed BF16 Data</td></tr><tr><td><a href='vcvtneps2bf16.html'>VCVTNEPS2BF16</a></td><td>Convert Packed Single Data to Packed BF16 Data</td></tr><tr><td><a href='vcvtpd2ph.html'>VCVTPD2PH</a></td><td>Convert Packed Double Precision FP Values to Packed FP16 Values</td></tr><tr><td><a href='vcvtpd2qq.html'>VCVTPD2QQ</a></td><td>Convert Packed Double Precision Floating-Point Values to Packed QuadwordIntegers</td></tr><tr><td><a href='vcvtpd2udq.html'>VCVTPD2UDQ</a></td><td>Convert Packed Double Precision Floating-Point Values to Packed UnsignedDoubleword Integers</td></tr><tr><td><a href='vcvtpd2uqq.html'>VCVTPD2UQQ</a></td><td>Convert Packed Double Precision Floating-Point Values to Packed UnsignedQuadword Integers</td></tr><tr><td><a href='vcvtph2dq.html'>VCVTPH2DQ</a></td><td>Convert Packed FP16 Values to Signed Doubleword Integers</td></tr><tr><td><a href='vcvtph2pd.html'>VCVTPH2PD</a></td><td>Convert Packed FP16 Values to FP64 Values</td></tr><tr><td><a href='vcvtph2ps.vcvtph2psx.html'>VCVTPH2PS</a></td><td>Convert Packed FP16 Values to Single Precision Floating-PointValues</td></tr><tr><td><a href='vcvtph2ps.vcvtph2psx.html'>VCVTPH2PSX</a></td><td>Convert Packed FP16 Values to Single Precision Floating-PointValues</td></tr><tr><td><a href='vcvtph2qq.html'>VCVTPH2QQ</a></td><td>Convert Packed FP16 Values to Signed Quadword Integer Values</td></tr><tr><td><a href='vcvtph2udq.html'>VCVTPH2UDQ</a></td><td>Convert Packed FP16 Values to Unsigned Doubleword Integers</td></tr><tr><td><a href='vcvtph2uqq.html'>VCVTPH2UQQ</a></td><td>Convert Packed FP16 Values to Unsigned Quadword Integers</td></tr><tr><td><a href='vcvtph2uw.html'>VCVTPH2UW</a></td><td>Convert Packed FP16 Values to Unsigned Word Integers</td></tr><tr><td><a href='vcvtph2w.html'>VCVTPH2W</a></td><td>Convert Packed FP16 Values to Signed Word Integers</td></tr><tr><td><a href='vcvtps2ph.html'>VCVTPS2PH</a></td><td>Convert Single-Precision FP Value to 16-bit FP Value</td></tr><tr><td><a href='vcvtps2phx.html'>VCVTPS2PHX</a></td><td>Convert Packed Single Precision Floating-Point Values to Packed FP16 Values</td></tr><tr><td><a href='vcvtps2qq.html'>VCVTPS2QQ</a></td><td>Convert Packed Single Precision Floating-Point Values to Packed SignedQuadword Integer Values</td></tr><tr><td><a href='vcvtps2udq.html'>VCVTPS2UDQ</a></td><td>Convert Packed Single Precision Floating-Point Values to Packed UnsignedDoubleword Integer Values</td></tr><tr><td><a href='vcvtps2uqq.html'>VCVTPS2UQQ</a></td><td>Convert Packed Single Precision Floating-Point Values to Packed UnsignedQuadword Integer Values</td></tr><tr><td><a href='vcvtqq2pd.html'>VCVTQQ2PD</a></td><td>Convert Packed Quadword Integers to Packed Double Precision Floating-PointValues</td></tr><tr><td><a href='vcvtqq2ph.html'>VCVTQQ2PH</a></td><td>Convert Packed Signed Quadword Integers to Packed FP16 Values</td></tr><tr><td><a href='vcvtqq2ps.html'>VCVTQQ2PS</a></td><td>Convert Packed Quadword Integers to Packed Single Precision Floating-PointValues</td></tr><tr><td><a href='vcvtsd2sh.html'>VCVTSD2SH</a></td><td>Convert Low FP64 Value to an FP16 Value</td></tr><tr><td><a href='vcvtsd2usi.html'>VCVTSD2USI</a></td><td>Convert Scalar Double Precision Floating-Point Value to Unsigned DoublewordInteger</td></tr><tr><td><a href='vcvtsh2sd.html'>VCVTSH2SD</a></td><td>Convert Low FP16 Value to an FP64 Value</td></tr><tr><td><a href='vcvtsh2si.html'>VCVTSH2SI</a></td><td>Convert Low FP16 Value to Signed Integer</td></tr><tr><td><a href='vcvtsh2ss.html'>VCVTSH2SS</a></td><td>Convert Low FP16 Value to FP32 Value</td></tr><tr><td><a href='vcvtsh2usi.html'>VCVTSH2USI</a></td><td>Convert Low FP16 Value to Unsigned Integer</td></tr><tr><td><a href='vcvtsi2sh.html'>VCVTSI2SH</a></td><td>Convert a Signed Doubleword/Quadword Integer to an FP16 Value</td></tr><tr><td><a href='vcvtss2sh.html'>VCVTSS2SH</a></td><td>Convert Low FP32 Value to an FP16 Value</td></tr><tr><td><a href='vcvtss2usi.html'>VCVTSS2USI</a></td><td>Convert Scalar Single Precision Floating-Point Value to Unsigned DoublewordInteger</td></tr><tr><td><a href='vcvttpd2qq.html'>VCVTTPD2QQ</a></td><td>Convert With Truncation Packed Double Precision Floating-Point Values toPacked Quadword Integers</td></tr><tr><td><a href='vcvttpd2udq.html'>VCVTTPD2UDQ</a></td><td>Convert With Truncation Packed Double Precision Floating-Point Values toPacked Unsigned Doubleword Integers</td></tr><tr><td><a href='vcvttpd2uqq.html'>VCVTTPD2UQQ</a></td><td>Convert With Truncation Packed Double Precision Floating-Point Values toPacked Unsigned Quadword Integers</td></tr><tr><td><a href='vcvttph2dq.html'>VCVTTPH2DQ</a></td><td>Convert with Truncation Packed FP16 Values to Signed Doubleword Integers</td></tr><tr><td><a href='vcvttph2qq.html'>VCVTTPH2QQ</a></td><td>Convert with Truncation Packed FP16 Values to Signed Quadword Integers</td></tr><tr><td><a href='vcvttph2udq.html'>VCVTTPH2UDQ</a></td><td>Convert with Truncation Packed FP16 Values to Unsigned DoublewordIntegers</td></tr><tr><td><a href='vcvttph2uqq.html'>VCVTTPH2UQQ</a></td><td>Convert with Truncation Packed FP16 Values to Unsigned Quadword Integers</td></tr><tr><td><a href='vcvttph2uw.html'>VCVTTPH2UW</a></td><td>Convert Packed FP16 Values to Unsigned Word Integers</td></tr><tr><td><a href='vcvttph2w.html'>VCVTTPH2W</a></td><td>Convert Packed FP16 Values to Signed Word Integers</td></tr><tr><td><a href='vcvttps2qq.html'>VCVTTPS2QQ</a></td><td>Convert With Truncation Packed Single Precision Floating-Point Values toPacked Signed Quadword Integer Values</td></tr><tr><td><a href='vcvttps2udq.html'>VCVTTPS2UDQ</a></td><td>Convert With Truncation Packed Single Precision Floating-Point Values toPacked Unsigned Doubleword Integer Values</td></tr><tr><td><a href='vcvttps2uqq.html'>VCVTTPS2UQQ</a></td><td>Convert With Truncation Packed Single Precision Floating-Point Values toPacked Unsigned Quadword Integer Values</td></tr><tr><td><a href='vcvttsd2usi.html'>VCVTTSD2USI</a></td><td>Convert With Truncation Scalar Double Precision Floating-Point Value toUnsigned Integer</td></tr><tr><td><a href='vcvttsh2si.html'>VCVTTSH2SI</a></td><td>Convert with Truncation Low FP16 Value to a Signed Integer</td></tr><tr><td><a href='vcvttsh2usi.html'>VCVTTSH2USI</a></td><td>Convert with Truncation Low FP16 Value to an Unsigned Integer</td></tr><tr><td><a href='vcvttss2usi.html'>VCVTTSS2USI</a></td><td>Convert With Truncation Scalar Single Precision Floating-Point Value toUnsigned Integer</td></tr><tr><td><a href='vcvtudq2pd.html'>VCVTUDQ2PD</a></td><td>Convert Packed Unsigned Doubleword Integers to Packed Double PrecisionFloating-Point Values</td></tr><tr><td><a href='vcvtudq2ph.html'>VCVTUDQ2PH</a></td><td>Convert Packed Unsigned Doubleword Integers to Packed FP16 Values</td></tr><tr><td><a href='vcvtudq2ps.html'>VCVTUDQ2PS</a></td><td>Convert Packed Unsigned Doubleword Integers to Packed Single PrecisionFloating-Point Values</td></tr><tr><td><a href='vcvtuqq2pd.html'>VCVTUQQ2PD</a></td><td>Convert Packed Unsigned Quadword Integers to Packed Double PrecisionFloating-Point Values</td></tr><tr><td><a href='vcvtuqq2ph.html'>VCVTUQQ2PH</a></td><td>Convert Packed Unsigned Quadword Integers to Packed FP16 Values</td></tr><tr><td><a href='vcvtuqq2ps.html'>VCVTUQQ2PS</a></td><td>Convert Packed Unsigned Quadword Integers to Packed Single PrecisionFloating-Point Values</td></tr><tr><td><a href='vcvtusi2sd.html'>VCVTUSI2SD</a></td><td>Convert Unsigned Integer to Scalar Double Precision Floating-Point Value</td></tr><tr><td><a href='vcvtusi2sh.html'>VCVTUSI2SH</a></td><td>Convert Unsigned Doubleword Integer to an FP16 Value</td></tr><tr><td><a href='vcvtusi2ss.html'>VCVTUSI2SS</a></td><td>Convert Unsigned Integer to Scalar Single Precision Floating-Point Value</td></tr><tr><td><a href='vcvtuw2ph.html'>VCVTUW2PH</a></td><td>Convert Packed Unsigned Word Integers to FP16 Values</td></tr><tr><td><a href='vcvtw2ph.html'>VCVTW2PH</a></td><td>Convert Packed Signed Word Integers to FP16 Values</td></tr><tr><td><a href='vdbpsadbw.html'>VDBPSADBW</a></td><td>Double Block Packed Sum-Absolute-Differences (SAD) on Unsigned Bytes</td></tr><tr><td><a href='vdivph.html'>VDIVPH</a></td><td>Divide Packed FP16 Values</td></tr><tr><td><a href='vdivsh.html'>VDIVSH</a></td><td>Divide Scalar FP16 Values</td></tr><tr><td><a href='vdpbf16ps.html'>VDPBF16PS</a></td><td>Dot Product of BF16 Pairs Accumulated Into Packed Single Precision</td></tr><tr><td><a href='verr.verw.html'>VERR</a></td><td>Verify a Segment for Reading or Writing</td></tr><tr><td><a href='verr.verw.html'>VERW</a></td><td>Verify a Segment for Reading or Writing</td></tr><tr><td><a href='vexpandpd.html'>VEXPANDPD</a></td><td>Load Sparse Packed Double Precision Floating-Point Values From Dense Memory</td></tr><tr><td><a href='vexpandps.html'>VEXPANDPS</a></td><td>Load Sparse Packed Single Precision Floating-Point Values From Dense Memory</td></tr><tr><td><a href='vextractf128.vextractf32x4.vextractf64x2.vextractf32x8.vextractf64x4.html'>VEXTRACTF128</a></td><td>Extract Packed Floating-Point Values</td></tr><tr><td><a href='vextractf128.vextractf32x4.vextractf64x2.vextractf32x8.vextractf64x4.html'>VEXTRACTF32x4</a></td><td>Extract Packed Floating-Point Values</td></tr><tr><td><a href='vextractf128.vextractf32x4.vextractf64x2.vextractf32x8.vextractf64x4.html'>VEXTRACTF32x8</a></td><td>Extract Packed Floating-Point Values</td></tr><tr><td><a href='vextractf128.vextractf32x4.vextractf64x2.vextractf32x8.vextractf64x4.html'>VEXTRACTF64x2</a></td><td>Extract Packed Floating-Point Values</td></tr><tr><td><a href='vextractf128.vextractf32x4.vextractf64x2.vextractf32x8.vextractf64x4.html'>VEXTRACTF64x4</a></td><td>Extract Packed Floating-Point Values</td></tr><tr><td><a href='vextracti128.vextracti32x4.vextracti64x2.vextracti32x8.vextracti64x4.html'>VEXTRACTI128</a></td><td>ExtractPacked Integer Values</td></tr><tr><td><a href='vextracti128.vextracti32x4.vextracti64x2.vextracti32x8.vextracti64x4.html'>VEXTRACTI32x4</a></td><td>ExtractPacked Integer Values</td></tr><tr><td><a href='vextracti128.vextracti32x4.vextracti64x2.vextracti32x8.vextracti64x4.html'>VEXTRACTI32x8</a></td><td>ExtractPacked Integer Values</td></tr><tr><td><a href='vextracti128.vextracti32x4.vextracti64x2.vextracti32x8.vextracti64x4.html'>VEXTRACTI64x2</a></td><td>ExtractPacked Integer Values</td></tr><tr><td><a href='vextracti128.vextracti32x4.vextracti64x2.vextracti32x8.vextracti64x4.html'>VEXTRACTI64x4</a></td><td>ExtractPacked Integer Values</td></tr><tr><td><a href='vfcmaddcph.vfmaddcph.html'>VFCMADDCPH</a></td><td>Complex Multiply and Accumulate FP16 Values</td></tr><tr><td><a href='vfcmaddcsh.vfmaddcsh.html'>VFCMADDCSH</a></td><td>Complex Multiply and Accumulate Scalar FP16 Values</td></tr><tr><td><a href='vfcmulcph.vfmulcph.html'>VFCMULCPH</a></td><td>Complex Multiply FP16 Values</td></tr><tr><td><a href='vfcmulcsh.vfmulcsh.html'>VFCMULCSH</a></td><td>Complex Multiply Scalar FP16 Values</td></tr><tr><td><a href='vfixupimmpd.html'>VFIXUPIMMPD</a></td><td>Fix Up Special Packed Float64 Values</td></tr><tr><td><a href='vfixupimmps.html'>VFIXUPIMMPS</a></td><td>Fix Up Special Packed Float32 Values</td></tr><tr><td><a href='vfixupimmsd.html'>VFIXUPIMMSD</a></td><td>Fix Up Special Scalar Float64 Value</td></tr><tr><td><a href='vfixupimmss.html'>VFIXUPIMMSS</a></td><td>Fix Up Special Scalar Float32 Value</td></tr><tr><td><a href='vfmadd132pd.vfmadd213pd.vfmadd231pd.html'>VFMADD132PD</a></td><td>Fused Multiply-Add of Packed DoublePrecision Floating-Point Values</td></tr><tr><td><a href='vfmadd132ph.vfnmadd132ph.vfmadd213ph.vfnmadd213ph.vfmadd231ph.vfnmadd231ph.html'>VFMADD132PH</a></td><td>Fused Multiply-Add of Packed FP16 Values</td></tr><tr><td><a href='vfmadd132ps.vfmadd213ps.vfmadd231ps.html'>VFMADD132PS</a></td><td>Fused Multiply-Add of Packed SinglePrecision Floating-Point Values</td></tr><tr><td><a href='vfmadd132sd.vfmadd213sd.vfmadd231sd.html'>VFMADD132SD</a></td><td>Fused Multiply-Add of Scalar DoublePrecision Floating-Point Values</td></tr><tr><td><a href='vfmadd132sh.vfnmadd132sh.vfmadd213sh.vfnmadd213sh.vfmadd231sh.vfnmadd231sh.html'>VFMADD132SH</a></td><td>Fused Multiply-Add of Scalar FP16 Values</td></tr><tr><td><a href='vfmadd132ss.vfmadd213ss.vfmadd231ss.html'>VFMADD132SS</a></td><td>Fused Multiply-Add of Scalar Single PrecisionFloating-Point Values</td></tr><tr><td><a href='vfmadd132pd.vfmadd213pd.vfmadd231pd.html'>VFMADD213PD</a></td><td>Fused Multiply-Add of Packed DoublePrecision Floating-Point Values</td></tr><tr><td><a href='vfmadd132ph.vfnmadd132ph.vfmadd213ph.vfnmadd213ph.vfmadd231ph.vfnmadd231ph.html'>VFMADD213PH</a></td><td>Fused Multiply-Add of Packed FP16 Values</td></tr><tr><td><a href='vfmadd132ps.vfmadd213ps.vfmadd231ps.html'>VFMADD213PS</a></td><td>Fused Multiply-Add of Packed SinglePrecision Floating-Point Values</td></tr><tr><td><a href='vfmadd132sd.vfmadd213sd.vfmadd231sd.html'>VFMADD213SD</a></td><td>Fused Multiply-Add of Scalar DoublePrecision Floating-Point Values</td></tr><tr><td><a href='vfmadd132sh.vfnmadd132sh.vfmadd213sh.vfnmadd213sh.vfmadd231sh.vfnmadd231sh.html'>VFMADD213SH</a></td><td>Fused Multiply-Add of Scalar FP16 Values</td></tr><tr><td><a href='vfmadd132ss.vfmadd213ss.vfmadd231ss.html'>VFMADD213SS</a></td><td>Fused Multiply-Add of Scalar Single PrecisionFloating-Point Values</td></tr><tr><td><a href='vfmadd132pd.vfmadd213pd.vfmadd231pd.html'>VFMADD231PD</a></td><td>Fused Multiply-Add of Packed DoublePrecision Floating-Point Values</td></tr><tr><td><a href='vfmadd132ph.vfnmadd132ph.vfmadd213ph.vfnmadd213ph.vfmadd231ph.vfnmadd231ph.html'>VFMADD231PH</a></td><td>Fused Multiply-Add of Packed FP16 Values</td></tr><tr><td><a href='vfmadd132ps.vfmadd213ps.vfmadd231ps.html'>VFMADD231PS</a></td><td>Fused Multiply-Add of Packed SinglePrecision Floating-Point Values</td></tr><tr><td><a href='vfmadd132sd.vfmadd213sd.vfmadd231sd.html'>VFMADD231SD</a></td><td>Fused Multiply-Add of Scalar DoublePrecision Floating-Point Values</td></tr><tr><td><a href='vfmadd132sh.vfnmadd132sh.vfmadd213sh.vfnmadd213sh.vfmadd231sh.vfnmadd231sh.html'>VFMADD231SH</a></td><td>Fused Multiply-Add of Scalar FP16 Values</td></tr><tr><td><a href='vfmadd132ss.vfmadd213ss.vfmadd231ss.html'>VFMADD231SS</a></td><td>Fused Multiply-Add of Scalar Single PrecisionFloating-Point Values</td></tr><tr><td><a href='vfcmaddcph.vfmaddcph.html'>VFMADDCPH</a></td><td>Complex Multiply and Accumulate FP16 Values</td></tr><tr><td><a href='vfcmaddcsh.vfmaddcsh.html'>VFMADDCSH</a></td><td>Complex Multiply and Accumulate Scalar FP16 Values</td></tr><tr><td><a href='vfmaddrnd231pd.html'>VFMADDRND231PD</a></td><td>Fused Multiply-Add of Packed Double-Precision Floating-Point Valueswith rounding control</td></tr><tr><td><a href='vfmaddsub132pd.vfmaddsub213pd.vfmaddsub231pd.html'>VFMADDSUB132PD</a></td><td>Fused Multiply-AlternatingAdd/Subtract of Packed Double Precision Floating-Point Values</td></tr><tr><td><a href='vfmaddsub132ph.vfmaddsub213ph.vfmaddsub231ph.html'>VFMADDSUB132PH</a></td><td>Fused Multiply-AlternatingAdd/Subtract of Packed FP16 Values</td></tr><tr><td><a href='vfmaddsub132ps.vfmaddsub213ps.vfmaddsub231ps.html'>VFMADDSUB132PS</a></td><td>Fused Multiply-AlternatingAdd/Subtract of Packed Single Precision Floating-Point Values</td></tr><tr><td><a href='vfmaddsub132pd.vfmaddsub213pd.vfmaddsub231pd.html'>VFMADDSUB213PD</a></td><td>Fused Multiply-AlternatingAdd/Subtract of Packed Double Precision Floating-Point Values</td></tr><tr><td><a href='vfmaddsub132ph.vfmaddsub213ph.vfmaddsub231ph.html'>VFMADDSUB213PH</a></td><td>Fused Multiply-AlternatingAdd/Subtract of Packed FP16 Values</td></tr><tr><td><a href='vfmaddsub132ps.vfmaddsub213ps.vfmaddsub231ps.html'>VFMADDSUB213PS</a></td><td>Fused Multiply-AlternatingAdd/Subtract of Packed Single Precision Floating-Point Values</td></tr><tr><td><a href='vfmaddsub132pd.vfmaddsub213pd.vfmaddsub231pd.html'>VFMADDSUB231PD</a></td><td>Fused Multiply-AlternatingAdd/Subtract of Packed Double Precision Floating-Point Values</td></tr><tr><td><a href='vfmaddsub132ph.vfmaddsub213ph.vfmaddsub231ph.html'>VFMADDSUB231PH</a></td><td>Fused Multiply-AlternatingAdd/Subtract of Packed FP16 Values</td></tr><tr><td><a href='vfmaddsub132ps.vfmaddsub213ps.vfmaddsub231ps.html'>VFMADDSUB231PS</a></td><td>Fused Multiply-AlternatingAdd/Subtract of Packed Single Precision Floating-Point Values</td></tr><tr><td><a href='vfmsub132pd.vfmsub213pd.vfmsub231pd.html'>VFMSUB132PD</a></td><td>Fused Multiply-Subtract of Packed DoublePrecision Floating-Point Values</td></tr><tr><td><a href='vfmsub132ph.vfnmsub132ph.vfmsub213ph.vfnmsub213ph.vfmsub231ph.vfnmsub231ph.html'>VFMSUB132PH</a></td><td>Fused Multiply-Subtract of Packed FP16 Values</td></tr><tr><td><a href='vfmsub132ps.vfmsub213ps.vfmsub231ps.html'>VFMSUB132PS</a></td><td>Fused Multiply-Subtract of Packed SinglePrecision Floating-Point Values</td></tr><tr><td><a href='vfmsub132sd.vfmsub213sd.vfmsub231sd.html'>VFMSUB132SD</a></td><td>Fused Multiply-Subtract of Scalar DoublePrecision Floating-Point Values</td></tr><tr><td><a href='vfmsub132sh.vfnmsub132sh.vfmsub213sh.vfnmsub213sh.vfmsub231sh.vfnmsub231sh.html'>VFMSUB132SH</a></td><td>Fused Multiply-Subtract of Scalar FP16 Values</td></tr><tr><td><a href='vfmsub132ss.vfmsub213ss.vfmsub231ss.html'>VFMSUB132SS</a></td><td>Fused Multiply-Subtract of Scalar SinglePrecision Floating-Point Values</td></tr><tr><td><a href='vfmsub132pd.vfmsub213pd.vfmsub231pd.html'>VFMSUB213PD</a></td><td>Fused Multiply-Subtract of Packed DoublePrecision Floating-Point Values</td></tr><tr><td><a href='vfmsub132ph.vfnmsub132ph.vfmsub213ph.vfnmsub213ph.vfmsub231ph.vfnmsub231ph.html'>VFMSUB213PH</a></td><td>Fused Multiply-Subtract of Packed FP16 Values</td></tr><tr><td><a href='vfmsub132ps.vfmsub213ps.vfmsub231ps.html'>VFMSUB213PS</a></td><td>Fused Multiply-Subtract of Packed SinglePrecision Floating-Point Values</td></tr><tr><td><a href='vfmsub132sd.vfmsub213sd.vfmsub231sd.html'>VFMSUB213SD</a></td><td>Fused Multiply-Subtract of Scalar DoublePrecision Floating-Point Values</td></tr><tr><td><a href='vfmsub132sh.vfnmsub132sh.vfmsub213sh.vfnmsub213sh.vfmsub231sh.vfnmsub231sh.html'>VFMSUB213SH</a></td><td>Fused Multiply-Subtract of Scalar FP16 Values</td></tr><tr><td><a href='vfmsub132ss.vfmsub213ss.vfmsub231ss.html'>VFMSUB213SS</a></td><td>Fused Multiply-Subtract of Scalar SinglePrecision Floating-Point Values</td></tr><tr><td><a href='vfmsub132pd.vfmsub213pd.vfmsub231pd.html'>VFMSUB231PD</a></td><td>Fused Multiply-Subtract of Packed DoublePrecision Floating-Point Values</td></tr><tr><td><a href='vfmsub132ph.vfnmsub132ph.vfmsub213ph.vfnmsub213ph.vfmsub231ph.vfnmsub231ph.html'>VFMSUB231PH</a></td><td>Fused Multiply-Subtract of Packed FP16 Values</td></tr><tr><td><a href='vfmsub132ps.vfmsub213ps.vfmsub231ps.html'>VFMSUB231PS</a></td><td>Fused Multiply-Subtract of Packed SinglePrecision Floating-Point Values</td></tr><tr><td><a href='vfmsub132sd.vfmsub213sd.vfmsub231sd.html'>VFMSUB231SD</a></td><td>Fused Multiply-Subtract of Scalar DoublePrecision Floating-Point Values</td></tr><tr><td><a href='vfmsub132sh.vfnmsub132sh.vfmsub213sh.vfnmsub213sh.vfmsub231sh.vfnmsub231sh.html'>VFMSUB231SH</a></td><td>Fused Multiply-Subtract of Scalar FP16 Values</td></tr><tr><td><a href='vfmsub132ss.vfmsub213ss.vfmsub231ss.html'>VFMSUB231SS</a></td><td>Fused Multiply-Subtract of Scalar SinglePrecision Floating-Point Values</td></tr><tr><td><a href='vfmsubadd132pd.vfmsubadd213pd.vfmsubadd231pd.html'>VFMSUBADD132PD</a></td><td>Fused Multiply-AlternatingSubtract/Add of Packed Double Precision Floating-Point Values</td></tr><tr><td><a href='vfmsubadd132ph.vfmsubadd213ph.vfmsubadd231ph.html'>VFMSUBADD132PH</a></td><td>Fused Multiply-AlternatingSubtract/Add of Packed FP16 Values</td></tr><tr><td><a href='vfmsubadd132ps.vfmsubadd213ps.vfmsubadd231ps.html'>VFMSUBADD132PS</a></td><td>Fused Multiply-AlternatingSubtract/Add of Packed Single Precision Floating-Point Values</td></tr><tr><td><a href='vfmsubadd132pd.vfmsubadd213pd.vfmsubadd231pd.html'>VFMSUBADD213PD</a></td><td>Fused Multiply-AlternatingSubtract/Add of Packed Double Precision Floating-Point Values</td></tr><tr><td><a href='vfmsubadd132ph.vfmsubadd213ph.vfmsubadd231ph.html'>VFMSUBADD213PH</a></td><td>Fused Multiply-AlternatingSubtract/Add of Packed FP16 Values</td></tr><tr><td><a href='vfmsubadd132ps.vfmsubadd213ps.vfmsubadd231ps.html'>VFMSUBADD213PS</a></td><td>Fused Multiply-AlternatingSubtract/Add of Packed Single Precision Floating-Point Values</td></tr><tr><td><a href='vfmsubadd132pd.vfmsubadd213pd.vfmsubadd231pd.html'>VFMSUBADD231PD</a></td><td>Fused Multiply-AlternatingSubtract/Add of Packed Double Precision Floating-Point Values</td></tr><tr><td><a href='vfmsubadd132ph.vfmsubadd213ph.vfmsubadd231ph.html'>VFMSUBADD231PH</a></td><td>Fused Multiply-AlternatingSubtract/Add of Packed FP16 Values</td></tr><tr><td><a href='vfmsubadd132ps.vfmsubadd213ps.vfmsubadd231ps.html'>VFMSUBADD231PS</a></td><td>Fused Multiply-AlternatingSubtract/Add of Packed Single Precision Floating-Point Values</td></tr><tr><td><a href='vfcmulcph.vfmulcph.html'>VFMULCPH</a></td><td>Complex Multiply FP16 Values</td></tr><tr><td><a href='vfcmulcsh.vfmulcsh.html'>VFMULCSH</a></td><td>Complex Multiply Scalar FP16 Values</td></tr><tr><td><a href='vfnmadd132pd.vfnmadd213pd.vfnmadd231pd.html'>VFNMADD132PD</a></td><td>Fused Negative Multiply-Add of PackedDouble Precision Floating-Point Values</td></tr><tr><td><a href='vfmadd132ph.vfnmadd132ph.vfmadd213ph.vfnmadd213ph.vfmadd231ph.vfnmadd231ph.html'>VFNMADD132PH</a></td><td>Fused Multiply-Add of Packed FP16 Values</td></tr><tr><td><a href='vfnmadd132ps.vfnmadd213ps.vfnmadd231ps.html'>VFNMADD132PS</a></td><td>Fused Negative Multiply-Add of PackedSingle Precision Floating-Point Values</td></tr><tr><td><a href='vfnmadd132sd.vfnmadd213sd.vfnmadd231sd.html'>VFNMADD132SD</a></td><td>Fused Negative Multiply-Add of ScalarDouble Precision Floating-Point Values</td></tr><tr><td><a href='vfmadd132sh.vfnmadd132sh.vfmadd213sh.vfnmadd213sh.vfmadd231sh.vfnmadd231sh.html'>VFNMADD132SH</a></td><td>Fused Multiply-Add of Scalar FP16 Values</td></tr><tr><td><a href='vfnmadd132ss.vfnmadd213ss.vfnmadd231ss.html'>VFNMADD132SS</a></td><td>Fused Negative Multiply-Add of ScalarSingle Precision Floating-Point Values</td></tr><tr><td><a href='vfnmadd132pd.vfnmadd213pd.vfnmadd231pd.html'>VFNMADD213PD</a></td><td>Fused Negative Multiply-Add of PackedDouble Precision Floating-Point Values</td></tr><tr><td><a href='vfmadd132ph.vfnmadd132ph.vfmadd213ph.vfnmadd213ph.vfmadd231ph.vfnmadd231ph.html'>VFNMADD213PH</a></td><td>Fused Multiply-Add of Packed FP16 Values</td></tr><tr><td><a href='vfnmadd132ps.vfnmadd213ps.vfnmadd231ps.html'>VFNMADD213PS</a></td><td>Fused Negative Multiply-Add of PackedSingle Precision Floating-Point Values</td></tr><tr><td><a href='vfnmadd132sd.vfnmadd213sd.vfnmadd231sd.html'>VFNMADD213SD</a></td><td>Fused Negative Multiply-Add of ScalarDouble Precision Floating-Point Values</td></tr><tr><td><a href='vfmadd132sh.vfnmadd132sh.vfmadd213sh.vfnmadd213sh.vfmadd231sh.vfnmadd231sh.html'>VFNMADD213SH</a></td><td>Fused Multiply-Add of Scalar FP16 Values</td></tr><tr><td><a href='vfnmadd132ss.vfnmadd213ss.vfnmadd231ss.html'>VFNMADD213SS</a></td><td>Fused Negative Multiply-Add of ScalarSingle Precision Floating-Point Values</td></tr><tr><td><a href='vfnmadd132pd.vfnmadd213pd.vfnmadd231pd.html'>VFNMADD231PD</a></td><td>Fused Negative Multiply-Add of PackedDouble Precision Floating-Point Values</td></tr><tr><td><a href='vfmadd132ph.vfnmadd132ph.vfmadd213ph.vfnmadd213ph.vfmadd231ph.vfnmadd231ph.html'>VFNMADD231PH</a></td><td>Fused Multiply-Add of Packed FP16 Values</td></tr><tr><td><a href='vfnmadd132ps.vfnmadd213ps.vfnmadd231ps.html'>VFNMADD231PS</a></td><td>Fused Negative Multiply-Add of PackedSingle Precision Floating-Point Values</td></tr><tr><td><a href='vfnmadd132sd.vfnmadd213sd.vfnmadd231sd.html'>VFNMADD231SD</a></td><td>Fused Negative Multiply-Add of ScalarDouble Precision Floating-Point Values</td></tr><tr><td><a href='vfmadd132sh.vfnmadd132sh.vfmadd213sh.vfnmadd213sh.vfmadd231sh.vfnmadd231sh.html'>VFNMADD231SH</a></td><td>Fused Multiply-Add of Scalar FP16 Values</td></tr><tr><td><a href='vfnmadd132ss.vfnmadd213ss.vfnmadd231ss.html'>VFNMADD231SS</a></td><td>Fused Negative Multiply-Add of ScalarSingle Precision Floating-Point Values</td></tr><tr><td><a href='vfnmsub132pd.vfnmsub213pd.vfnmsub231pd.html'>VFNMSUB132PD</a></td><td>Fused Negative Multiply-Subtract ofPacked Double Precision Floating-Point Values</td></tr><tr><td><a href='vfmsub132ph.vfnmsub132ph.vfmsub213ph.vfnmsub213ph.vfmsub231ph.vfnmsub231ph.html'>VFNMSUB132PH</a></td><td>Fused Multiply-Subtract of Packed FP16 Values</td></tr><tr><td><a href='vfnmsub132ps.vfnmsub213ps.vfnmsub231ps.html'>VFNMSUB132PS</a></td><td>Fused Negative Multiply-Subtract ofPacked Single Precision Floating-Point Values</td></tr><tr><td><a href='vfnmsub132sd.vfnmsub213sd.vfnmsub231sd.html'>VFNMSUB132SD</a></td><td>Fused Negative Multiply-Subtract ofScalar Double Precision Floating-Point Values</td></tr><tr><td><a href='vfmsub132sh.vfnmsub132sh.vfmsub213sh.vfnmsub213sh.vfmsub231sh.vfnmsub231sh.html'>VFNMSUB132SH</a></td><td>Fused Multiply-Subtract of Scalar FP16 Values</td></tr><tr><td><a href='vfnmsub132ss.vfnmsub213ss.vfnmsub231ss.html'>VFNMSUB132SS</a></td><td>Fused Negative Multiply-Subtract ofScalar Single Precision Floating-Point Values</td></tr><tr><td><a href='vfnmsub132pd.vfnmsub213pd.vfnmsub231pd.html'>VFNMSUB213PD</a></td><td>Fused Negative Multiply-Subtract ofPacked Double Precision Floating-Point Values</td></tr><tr><td><a href='vfmsub132ph.vfnmsub132ph.vfmsub213ph.vfnmsub213ph.vfmsub231ph.vfnmsub231ph.html'>VFNMSUB213PH</a></td><td>Fused Multiply-Subtract of Packed FP16 Values</td></tr><tr><td><a href='vfnmsub132ps.vfnmsub213ps.vfnmsub231ps.html'>VFNMSUB213PS</a></td><td>Fused Negative Multiply-Subtract ofPacked Single Precision Floating-Point Values</td></tr><tr><td><a href='vfnmsub132sd.vfnmsub213sd.vfnmsub231sd.html'>VFNMSUB213SD</a></td><td>Fused Negative Multiply-Subtract ofScalar Double Precision Floating-Point Values</td></tr><tr><td><a href='vfmsub132sh.vfnmsub132sh.vfmsub213sh.vfnmsub213sh.vfmsub231sh.vfnmsub231sh.html'>VFNMSUB213SH</a></td><td>Fused Multiply-Subtract of Scalar FP16 Values</td></tr><tr><td><a href='vfnmsub132ss.vfnmsub213ss.vfnmsub231ss.html'>VFNMSUB213SS</a></td><td>Fused Negative Multiply-Subtract ofScalar Single Precision Floating-Point Values</td></tr><tr><td><a href='vfnmsub132pd.vfnmsub213pd.vfnmsub231pd.html'>VFNMSUB231PD</a></td><td>Fused Negative Multiply-Subtract ofPacked Double Precision Floating-Point Values</td></tr><tr><td><a href='vfmsub132ph.vfnmsub132ph.vfmsub213ph.vfnmsub213ph.vfmsub231ph.vfnmsub231ph.html'>VFNMSUB231PH</a></td><td>Fused Multiply-Subtract of Packed FP16 Values</td></tr><tr><td><a href='vfnmsub132ps.vfnmsub213ps.vfnmsub231ps.html'>VFNMSUB231PS</a></td><td>Fused Negative Multiply-Subtract ofPacked Single Precision Floating-Point Values</td></tr><tr><td><a href='vfnmsub132sd.vfnmsub213sd.vfnmsub231sd.html'>VFNMSUB231SD</a></td><td>Fused Negative Multiply-Subtract ofScalar Double Precision Floating-Point Values</td></tr><tr><td><a href='vfmsub132sh.vfnmsub132sh.vfmsub213sh.vfnmsub213sh.vfmsub231sh.vfnmsub231sh.html'>VFNMSUB231SH</a></td><td>Fused Multiply-Subtract of Scalar FP16 Values</td></tr><tr><td><a href='vfnmsub132ss.vfnmsub213ss.vfnmsub231ss.html'>VFNMSUB231SS</a></td><td>Fused Negative Multiply-Subtract ofScalar Single Precision Floating-Point Values</td></tr><tr><td><a href='vfpclasspd.html'>VFPCLASSPD</a></td><td>Tests Types of Packed Float64 Values</td></tr><tr><td><a href='vfpclassph.html'>VFPCLASSPH</a></td><td>Test Types of Packed FP16 Values</td></tr><tr><td><a href='vfpclassps.html'>VFPCLASSPS</a></td><td>Tests Types of Packed Float32 Values</td></tr><tr><td><a href='vfpclasssd.html'>VFPCLASSSD</a></td><td>Tests Type of a Scalar Float64 Value</td></tr><tr><td><a href='vfpclasssh.html'>VFPCLASSSH</a></td><td>Test Types of Scalar FP16 Values</td></tr><tr><td><a href='vfpclassss.html'>VFPCLASSSS</a></td><td>Tests Type of a Scalar Float32 Value</td></tr><tr><td><a href='vgatherdpd.vgatherqpd.html'>VGATHERDPD</a></td><td>Gather Packed Double Precision Floating-Point Values UsingSigned Dword/Qword Indices</td></tr><tr><td><a href='vgatherdps.vgatherdpd.html'>VGATHERDPD</a> (1)</td><td>Gather Packed Single, Packed Double with Signed Dword Indices</td></tr><tr><td><a href='vgatherdps.vgatherqps.html'>VGATHERDPS</a></td><td>Gather Packed Single Precision Floating-Point Values UsingSigned Dword/Qword Indices</td></tr><tr><td><a href='vgatherdps.vgatherdpd.html'>VGATHERDPS</a> (1)</td><td>Gather Packed Single, Packed Double with Signed Dword Indices</td></tr><tr><td><a href='vgatherdpd.vgatherqpd.html'>VGATHERQPD</a></td><td>Gather Packed Double Precision Floating-Point Values UsingSigned Dword/Qword Indices</td></tr><tr><td><a href='vgatherqps.vgatherqpd.html'>VGATHERQPD</a> (1)</td><td>Gather Packed Single, Packed Double with Signed Qword Indices</td></tr><tr><td><a href='vgatherdps.vgatherqps.html'>VGATHERQPS</a></td><td>Gather Packed Single Precision Floating-Point Values UsingSigned Dword/Qword Indices</td></tr><tr><td><a href='vgatherqps.vgatherqpd.html'>VGATHERQPS</a> (1)</td><td>Gather Packed Single, Packed Double with Signed Qword Indices</td></tr><tr><td><a href='vgetexppd.html'>VGETEXPPD</a></td><td>Convert Exponents of Packed Double Precision Floating-Point Values to DoublePrecision Floating-Point Values</td></tr><tr><td><a href='vgetexpph.html'>VGETEXPPH</a></td><td>Convert Exponents of Packed FP16 Values to FP16 Values</td></tr><tr><td><a href='vgetexpps.html'>VGETEXPPS</a></td><td>Convert Exponents of Packed Single Precision Floating-Point Values to SinglePrecision Floating-Point Values</td></tr><tr><td><a href='vgetexpsd.html'>VGETEXPSD</a></td><td>Convert Exponents of Scalar Double Precision Floating-Point Value to DoublePrecision Floating-Point Value</td></tr><tr><td><a href='vgetexpsh.html'>VGETEXPSH</a></td><td>Convert Exponents of Scalar FP16 Values to FP16 Values</td></tr><tr><td><a href='vgetexpss.html'>VGETEXPSS</a></td><td>Convert Exponents of Scalar Single Precision Floating-Point Value to SinglePrecision Floating-Point Value</td></tr><tr><td><a href='vgetmantpd.html'>VGETMANTPD</a></td><td>Extract Float64 Vector of Normalized Mantissas From Float64 Vector</td></tr><tr><td><a href='vgetmantph.html'>VGETMANTPH</a></td><td>Extract FP16 Vector of Normalized Mantissas from FP16 Vector</td></tr><tr><td><a href='vgetmantps.html'>VGETMANTPS</a></td><td>Extract Float32 Vector of Normalized Mantissas From Float32 Vector</td></tr><tr><td><a href='vgetmantsd.html'>VGETMANTSD</a></td><td>Extract Float64 of Normalized Mantissa From Float64 Scalar</td></tr><tr><td><a href='vgetmantsh.html'>VGETMANTSH</a></td><td>Extract FP16 of Normalized Mantissa from FP16 Scalar</td></tr><tr><td><a href='vgetmantss.html'>VGETMANTSS</a></td><td>Extract Float32 Vector of Normalized Mantissa From Float32 Scalar</td></tr><tr><td><a href='vinsertf128.vinsertf32x4.vinsertf64x2.vinsertf32x8.vinsertf64x4.html'>VINSERTF128</a></td><td>Insert PackedFloating-Point Values</td></tr><tr><td><a href='vinsertf128.vinsertf32x4.vinsertf64x2.vinsertf32x8.vinsertf64x4.html'>VINSERTF32x4</a></td><td>Insert PackedFloating-Point Values</td></tr><tr><td><a href='vinsertf128.vinsertf32x4.vinsertf64x2.vinsertf32x8.vinsertf64x4.html'>VINSERTF32x8</a></td><td>Insert PackedFloating-Point Values</td></tr><tr><td><a href='vinsertf128.vinsertf32x4.vinsertf64x2.vinsertf32x8.vinsertf64x4.html'>VINSERTF64x2</a></td><td>Insert PackedFloating-Point Values</td></tr><tr><td><a href='vinsertf128.vinsertf32x4.vinsertf64x2.vinsertf32x8.vinsertf64x4.html'>VINSERTF64x4</a></td><td>Insert PackedFloating-Point Values</td></tr><tr><td><a href='vinserti128.vinserti32x4.vinserti64x2.vinserti32x8.vinserti64x4.html'>VINSERTI128</a></td><td>Insert PackedInteger Values</td></tr><tr><td><a href='vinserti128.vinserti32x4.vinserti64x2.vinserti32x8.vinserti64x4.html'>VINSERTI32x4</a></td><td>Insert PackedInteger Values</td></tr><tr><td><a href='vinserti128.vinserti32x4.vinserti64x2.vinserti32x8.vinserti64x4.html'>VINSERTI32x8</a></td><td>Insert PackedInteger Values</td></tr><tr><td><a href='vinserti128.vinserti32x4.vinserti64x2.vinserti32x8.vinserti64x4.html'>VINSERTI64x2</a></td><td>Insert PackedInteger Values</td></tr><tr><td><a href='vinserti128.vinserti32x4.vinserti64x2.vinserti32x8.vinserti64x4.html'>VINSERTI64x4</a></td><td>Insert PackedInteger Values</td></tr><tr><td><a href='vmaskmov.html'>VMASKMOV</a></td><td>Conditional SIMD Packed Loads and Stores</td></tr><tr><td><a href='vmaxph.html'>VMAXPH</a></td><td>Return Maximum of Packed FP16 Values</td></tr><tr><td><a href='vmaxsh.html'>VMAXSH</a></td><td>Return Maximum of Scalar FP16 Values</td></tr><tr><td><a href='vminph.html'>VMINPH</a></td><td>Return Minimum of Packed FP16 Values</td></tr><tr><td><a href='vminsh.html'>VMINSH</a></td><td>Return Minimum Scalar FP16 Value</td></tr><tr><td><a href='movdqa.vmovdqa32.vmovdqa64.html'>VMOVDQA32</a></td><td>Move Aligned Packed Integer Values</td></tr><tr><td><a href='movdqa.vmovdqa32.vmovdqa64.html'>VMOVDQA64</a></td><td>Move Aligned Packed Integer Values</td></tr><tr><td><a href='movdqu.vmovdqu8.vmovdqu16.vmovdqu32.vmovdqu64.html'>VMOVDQU16</a></td><td>Move Unaligned Packed Integer Values</td></tr><tr><td><a href='movdqu.vmovdqu8.vmovdqu16.vmovdqu32.vmovdqu64.html'>VMOVDQU32</a></td><td>Move Unaligned Packed Integer Values</td></tr><tr><td><a href='movdqu.vmovdqu8.vmovdqu16.vmovdqu32.vmovdqu64.html'>VMOVDQU64</a></td><td>Move Unaligned Packed Integer Values</td></tr><tr><td><a href='movdqu.vmovdqu8.vmovdqu16.vmovdqu32.vmovdqu64.html'>VMOVDQU8</a></td><td>Move Unaligned Packed Integer Values</td></tr><tr><td><a href='vmovsh.html'>VMOVSH</a></td><td>Move Scalar FP16 Value</td></tr><tr><td><a href='vmovw.html'>VMOVW</a></td><td>Move Word</td></tr><tr><td><a href='vmulph.html'>VMULPH</a></td><td>Multiply Packed FP16 Values</td></tr><tr><td><a href='vmulsh.html'>VMULSH</a></td><td>Multiply Scalar FP16 Values</td></tr><tr><td><a href='vp2intersectd.vp2intersectq.html'>VP2INTERSECTD</a></td><td>Compute Intersection Between DWORDS/QUADWORDS to aPair of Mask Registers</td></tr><tr><td><a href='vp2intersectd.vp2intersectq.html'>VP2INTERSECTQ</a></td><td>Compute Intersection Between DWORDS/QUADWORDS to aPair of Mask Registers</td></tr><tr><td><a href='vpblendd.html'>VPBLENDD</a></td><td>Blend Packed Dwords</td></tr><tr><td><a href='vpblendmb.vpblendmw.html'>VPBLENDMB</a></td><td>Blend Byte/Word Vectors Using an Opmask Control</td></tr><tr><td><a href='vpblendmd.vpblendmq.html'>VPBLENDMD</a></td><td>Blend Int32/Int64 Vectors Using an OpMask Control</td></tr><tr><td><a href='vpblendmd.vpblendmq.html'>VPBLENDMQ</a></td><td>Blend Int32/Int64 Vectors Using an OpMask Control</td></tr><tr><td><a href='vpblendmb.vpblendmw.html'>VPBLENDMW</a></td><td>Blend Byte/Word Vectors Using an Opmask Control</td></tr><tr><td><a href='vpbroadcast.html'>VPBROADCAST</a></td><td>Load Integer and Broadcast</td></tr><tr><td><a href='vpbroadcastb.vpbroadcastw.vpbroadcastd.vpbroadcastq.html'>VPBROADCASTB</a></td><td>Load With Broadcast Integer Data From General Purpose Register</td></tr><tr><td><a href='vpbroadcastb.vpbroadcastw.vpbroadcastd.vpbroadcastq.html'>VPBROADCASTD</a></td><td>Load With Broadcast Integer Data From General Purpose Register</td></tr><tr><td><a href='vpbroadcastm.html'>VPBROADCASTM</a></td><td>Broadcast Mask to Vector Register</td></tr><tr><td><a href='vpbroadcastb.vpbroadcastw.vpbroadcastd.vpbroadcastq.html'>VPBROADCASTQ</a></td><td>Load With Broadcast Integer Data From General Purpose Register</td></tr><tr><td><a href='vpbroadcastb.vpbroadcastw.vpbroadcastd.vpbroadcastq.html'>VPBROADCASTW</a></td><td>Load With Broadcast Integer Data From General Purpose Register</td></tr><tr><td><a href='vpcmpb.vpcmpub.html'>VPCMPB</a></td><td>Compare Packed Byte Values Into Mask</td></tr><tr><td><a href='vpcmpd.vpcmpud.html'>VPCMPD</a></td><td>Compare Packed Integer Values Into Mask</td></tr><tr><td><a href='vpcmpq.vpcmpuq.html'>VPCMPQ</a></td><td>Compare Packed Integer Values Into Mask</td></tr><tr><td><a href='vpcmpb.vpcmpub.html'>VPCMPUB</a></td><td>Compare Packed Byte Values Into Mask</td></tr><tr><td><a href='vpcmpd.vpcmpud.html'>VPCMPUD</a></td><td>Compare Packed Integer Values Into Mask</td></tr><tr><td><a href='vpcmpq.vpcmpuq.html'>VPCMPUQ</a></td><td>Compare Packed Integer Values Into Mask</td></tr><tr><td><a href='vpcmpw.vpcmpuw.html'>VPCMPUW</a></td><td>Compare Packed Word Values Into Mask</td></tr><tr><td><a href='vpcmpw.vpcmpuw.html'>VPCMPW</a></td><td>Compare Packed Word Values Into Mask</td></tr><tr><td><a href='vpcompressb.vcompressw.html'>VPCOMPRESSB</a></td><td>Store Sparse Packed Byte/Word Integer Values Into DenseMemory/Register</td></tr><tr><td><a href='vpcompressd.html'>VPCOMPRESSD</a></td><td>Store Sparse Packed Doubleword Integer Values Into Dense Memory/Register</td></tr><tr><td><a href='vpcompressq.html'>VPCOMPRESSQ</a></td><td>Store Sparse Packed Quadword Integer Values Into Dense Memory/Register</td></tr><tr><td><a href='vpconflictd.vpconflictq.html'>VPCONFLICTD</a></td><td>Detect Conflicts Within a Vector of Packed Dword/Qword Values Into DenseMemory/ Register</td></tr><tr><td><a href='vpconflictd.vpconflictq.html'>VPCONFLICTQ</a></td><td>Detect Conflicts Within a Vector of Packed Dword/Qword Values Into DenseMemory/ Register</td></tr><tr><td><a href='vpdpbusd.html'>VPDPBUSD</a></td><td>Multiply and Add Unsigned and Signed Bytes</td></tr><tr><td><a href='vpdpbusds.html'>VPDPBUSDS</a></td><td>Multiply and Add Unsigned and Signed Bytes With Saturation</td></tr><tr><td><a href='vpdpwssd.html'>VPDPWSSD</a></td><td>Multiply and Add Signed Word Integers</td></tr><tr><td><a href='vpdpwssds.html'>VPDPWSSDS</a></td><td>Multiply and Add Signed Word Integers With Saturation</td></tr><tr><td><a href='vperm2f128.html'>VPERM2F128</a></td><td>Permute Floating-Point Values</td></tr><tr><td><a href='vperm2i128.html'>VPERM2I128</a></td><td>Permute Integer Values</td></tr><tr><td><a href='vpermb.html'>VPERMB</a></td><td>Permute Packed Bytes Elements</td></tr><tr><td><a href='vpermd.vpermw.html'>VPERMD</a></td><td>Permute Packed Doubleword/Word Elements</td></tr><tr><td><a href='vpermi2b.html'>VPERMI2B</a></td><td>Full Permute of Bytes From Two Tables Overwriting the Index</td></tr><tr><td><a href='vpermi2w.vpermi2d.vpermi2q.vpermi2ps.vpermi2pd.html'>VPERMI2D</a></td><td>Full Permute From Two Tables Overwriting the Index</td></tr><tr><td><a href='vpermi2w.vpermi2d.vpermi2q.vpermi2ps.vpermi2pd.html'>VPERMI2PD</a></td><td>Full Permute From Two Tables Overwriting the Index</td></tr><tr><td><a href='vpermi2w.vpermi2d.vpermi2q.vpermi2ps.vpermi2pd.html'>VPERMI2PS</a></td><td>Full Permute From Two Tables Overwriting the Index</td></tr><tr><td><a href='vpermi2w.vpermi2d.vpermi2q.vpermi2ps.vpermi2pd.html'>VPERMI2Q</a></td><td>Full Permute From Two Tables Overwriting the Index</td></tr><tr><td><a href='vpermi2w.vpermi2d.vpermi2q.vpermi2ps.vpermi2pd.html'>VPERMI2W</a></td><td>Full Permute From Two Tables Overwriting the Index</td></tr><tr><td><a href='vpermilpd.html'>VPERMILPD</a></td><td>Permute In-Lane of Pairs of Double Precision Floating-Point Values</td></tr><tr><td><a href='vpermilps.html'>VPERMILPS</a></td><td>Permute In-Lane of Quadruples of Single Precision Floating-Point Values</td></tr><tr><td><a href='vpermpd.html'>VPERMPD</a></td><td>Permute Double Precision Floating-Point Elements</td></tr><tr><td><a href='vpermps.html'>VPERMPS</a></td><td>Permute Single Precision Floating-Point Elements</td></tr><tr><td><a href='vpermq.html'>VPERMQ</a></td><td>Qwords Element Permutation</td></tr><tr><td><a href='vpermt2b.html'>VPERMT2B</a></td><td>Full Permute of Bytes From Two Tables Overwriting a Table</td></tr><tr><td><a href='vpermt2w.vpermt2d.vpermt2q.vpermt2ps.vpermt2pd.html'>VPERMT2D</a></td><td>Full Permute From Two Tables Overwriting One Table</td></tr><tr><td><a href='vpermt2w.vpermt2d.vpermt2q.vpermt2ps.vpermt2pd.html'>VPERMT2PD</a></td><td>Full Permute From Two Tables Overwriting One Table</td></tr><tr><td><a href='vpermt2w.vpermt2d.vpermt2q.vpermt2ps.vpermt2pd.html'>VPERMT2PS</a></td><td>Full Permute From Two Tables Overwriting One Table</td></tr><tr><td><a href='vpermt2w.vpermt2d.vpermt2q.vpermt2ps.vpermt2pd.html'>VPERMT2Q</a></td><td>Full Permute From Two Tables Overwriting One Table</td></tr><tr><td><a href='vpermt2w.vpermt2d.vpermt2q.vpermt2ps.vpermt2pd.html'>VPERMT2W</a></td><td>Full Permute From Two Tables Overwriting One Table</td></tr><tr><td><a href='vpermd.vpermw.html'>VPERMW</a></td><td>Permute Packed Doubleword/Word Elements</td></tr><tr><td><a href='vpexpandb.vpexpandw.html'>VPEXPANDB</a></td><td>Expand Byte/Word Values</td></tr><tr><td><a href='vpexpandd.html'>VPEXPANDD</a></td><td>Load Sparse Packed Doubleword Integer Values From Dense Memory/Register</td></tr><tr><td><a href='vpexpandq.html'>VPEXPANDQ</a></td><td>Load Sparse Packed Quadword Integer Values From Dense Memory/Register</td></tr><tr><td><a href='vpexpandb.vpexpandw.html'>VPEXPANDW</a></td><td>Expand Byte/Word Values</td></tr><tr><td><a href='vpgatherdd.vpgatherqd.html'>VPGATHERDD</a></td><td>Gather Packed Dword Values Using Signed Dword/Qword Indices</td></tr><tr><td><a href='vpgatherdd.vpgatherdq.html'>VPGATHERDD</a> (1)</td><td>Gather Packed Dword, Packed Qword With Signed Dword Indices</td></tr><tr><td><a href='vpgatherdd.vpgatherdq.html'>VPGATHERDQ</a></td><td>Gather Packed Dword, Packed Qword With Signed Dword Indices</td></tr><tr><td><a href='vpgatherdq.vpgatherqq.html'>VPGATHERDQ</a> (1)</td><td>Gather Packed Qword Values Using Signed Dword/Qword Indices</td></tr><tr><td><a href='vpgatherdd.vpgatherqd.html'>VPGATHERQD</a></td><td>Gather Packed Dword Values Using Signed Dword/Qword Indices</td></tr><tr><td><a href='vpgatherqd.vpgatherqq.html'>VPGATHERQD</a> (1)</td><td>Gather Packed Dword, Packed Qword with Signed Qword Indices</td></tr><tr><td><a href='vpgatherdq.vpgatherqq.html'>VPGATHERQQ</a></td><td>Gather Packed Qword Values Using Signed Dword/Qword Indices</td></tr><tr><td><a href='vpgatherqd.vpgatherqq.html'>VPGATHERQQ</a> (1)</td><td>Gather Packed Dword, Packed Qword with Signed Qword Indices</td></tr><tr><td><a href='vplzcntd.vplzcntq.html'>VPLZCNTD</a></td><td>Count the Number of Leading Zero Bits for Packed Dword, Packed Qword Values</td></tr><tr><td><a href='vplzcntd.vplzcntq.html'>VPLZCNTQ</a></td><td>Count the Number of Leading Zero Bits for Packed Dword, Packed Qword Values</td></tr><tr><td><a href='vpmadd52huq.html'>VPMADD52HUQ</a></td><td>Packed Multiply of Unsigned 52-Bit Unsigned Integers and Add High 52-BitProducts to 64-Bit Accumulators</td></tr><tr><td><a href='vpmadd52luq.html'>VPMADD52LUQ</a></td><td>Packed Multiply of Unsigned 52-Bit Integers and Add the Low 52-Bit Productsto Qword Accumulators</td></tr><tr><td><a href='vpmaskmov.html'>VPMASKMOV</a></td><td>Conditional SIMD Integer Packed Loads and Stores</td></tr><tr><td><a href='vpmovb2m.vpmovw2m.vpmovd2m.vpmovq2m.html'>VPMOVB2M</a></td><td>Convert a Vector Register to a Mask</td></tr><tr><td><a href='vpmovb2m.vpmovw2m.vpmovd2m.vpmovq2m.html'>VPMOVD2M</a></td><td>Convert a Vector Register to a Mask</td></tr><tr><td><a href='vpmovdb.vpmovsdb.vpmovusdb.html'>VPMOVDB</a></td><td>Down Convert DWord to Byte</td></tr><tr><td><a href='vpmovdw.vpmovsdw.vpmovusdw.html'>VPMOVDW</a></td><td>Down Convert DWord to Word</td></tr><tr><td><a href='vpmovm2b.vpmovm2w.vpmovm2d.vpmovm2q.html'>VPMOVM2B</a></td><td>Convert a Mask Register to a VectorRegister</td></tr><tr><td><a href='vpmovm2b.vpmovm2w.vpmovm2d.vpmovm2q.html'>VPMOVM2D</a></td><td>Convert a Mask Register to a VectorRegister</td></tr><tr><td><a href='vpmovm2b.vpmovm2w.vpmovm2d.vpmovm2q.html'>VPMOVM2Q</a></td><td>Convert a Mask Register to a VectorRegister</td></tr><tr><td><a href='vpmovm2b.vpmovm2w.vpmovm2d.vpmovm2q.html'>VPMOVM2W</a></td><td>Convert a Mask Register to a VectorRegister</td></tr><tr><td><a href='vpmovb2m.vpmovw2m.vpmovd2m.vpmovq2m.html'>VPMOVQ2M</a></td><td>Convert a Vector Register to a Mask</td></tr><tr><td><a href='vpmovqb.vpmovsqb.vpmovusqb.html'>VPMOVQB</a></td><td>Down Convert QWord to Byte</td></tr><tr><td><a href='vpmovqd.vpmovsqd.vpmovusqd.html'>VPMOVQD</a></td><td>Down Convert QWord to DWord</td></tr><tr><td><a href='vpmovqw.vpmovsqw.vpmovusqw.html'>VPMOVQW</a></td><td>Down Convert QWord to Word</td></tr><tr><td><a href='vpmovdb.vpmovsdb.vpmovusdb.html'>VPMOVSDB</a></td><td>Down Convert DWord to Byte</td></tr><tr><td><a href='vpmovdw.vpmovsdw.vpmovusdw.html'>VPMOVSDW</a></td><td>Down Convert DWord to Word</td></tr><tr><td><a href='vpmovqb.vpmovsqb.vpmovusqb.html'>VPMOVSQB</a></td><td>Down Convert QWord to Byte</td></tr><tr><td><a href='vpmovqd.vpmovsqd.vpmovusqd.html'>VPMOVSQD</a></td><td>Down Convert QWord to DWord</td></tr><tr><td><a href='vpmovqw.vpmovsqw.vpmovusqw.html'>VPMOVSQW</a></td><td>Down Convert QWord to Word</td></tr><tr><td><a href='vpmovwb.vpmovswb.vpmovuswb.html'>VPMOVSWB</a></td><td>Down Convert Word to Byte</td></tr><tr><td><a href='vpmovdb.vpmovsdb.vpmovusdb.html'>VPMOVUSDB</a></td><td>Down Convert DWord to Byte</td></tr><tr><td><a href='vpmovdw.vpmovsdw.vpmovusdw.html'>VPMOVUSDW</a></td><td>Down Convert DWord to Word</td></tr><tr><td><a href='vpmovqb.vpmovsqb.vpmovusqb.html'>VPMOVUSQB</a></td><td>Down Convert QWord to Byte</td></tr><tr><td><a href='vpmovqd.vpmovsqd.vpmovusqd.html'>VPMOVUSQD</a></td><td>Down Convert QWord to DWord</td></tr><tr><td><a href='vpmovqw.vpmovsqw.vpmovusqw.html'>VPMOVUSQW</a></td><td>Down Convert QWord to Word</td></tr><tr><td><a href='vpmovwb.vpmovswb.vpmovuswb.html'>VPMOVUSWB</a></td><td>Down Convert Word to Byte</td></tr><tr><td><a href='vpmovb2m.vpmovw2m.vpmovd2m.vpmovq2m.html'>VPMOVW2M</a></td><td>Convert a Vector Register to a Mask</td></tr><tr><td><a href='vpmovwb.vpmovswb.vpmovuswb.html'>VPMOVWB</a></td><td>Down Convert Word to Byte</td></tr><tr><td><a href='vpmultishiftqb.html'>VPMULTISHIFTQB</a></td><td>Select Packed Unaligned Bytes From Quadword Sources</td></tr><tr><td><a href='vpopcnt.html'>VPOPCNT</a></td><td>Return the Count of Number of Bits Set to 1 in BYTE/WORD/DWORD/QWORD</td></tr><tr><td><a href='vprold.vprolvd.vprolq.vprolvq.html'>VPROLD</a></td><td>Bit Rotate Left</td></tr><tr><td><a href='vprold.vprolvd.vprolq.vprolvq.html'>VPROLQ</a></td><td>Bit Rotate Left</td></tr><tr><td><a href='vprold.vprolvd.vprolq.vprolvq.html'>VPROLVD</a></td><td>Bit Rotate Left</td></tr><tr><td><a href='vprold.vprolvd.vprolq.vprolvq.html'>VPROLVQ</a></td><td>Bit Rotate Left</td></tr><tr><td><a href='vprord.vprorvd.vprorq.vprorvq.html'>VPRORD</a></td><td>Bit Rotate Right</td></tr><tr><td><a href='vprord.vprorvd.vprorq.vprorvq.html'>VPRORQ</a></td><td>Bit Rotate Right</td></tr><tr><td><a href='vprord.vprorvd.vprorq.vprorvq.html'>VPRORVD</a></td><td>Bit Rotate Right</td></tr><tr><td><a href='vprord.vprorvd.vprorq.vprorvq.html'>VPRORVQ</a></td><td>Bit Rotate Right</td></tr><tr><td><a href='vpscatterdd.vpscatterdq.vpscatterqd.vpscatterqq.html'>VPSCATTERDD</a></td><td>Scatter Packed Dword, PackedQword with Signed Dword, Signed Qword Indices</td></tr><tr><td><a href='vpscatterdd.vpscatterdq.vpscatterqd.vpscatterqq.html'>VPSCATTERDQ</a></td><td>Scatter Packed Dword, PackedQword with Signed Dword, Signed Qword Indices</td></tr><tr><td><a href='vpscatterdd.vpscatterdq.vpscatterqd.vpscatterqq.html'>VPSCATTERQD</a></td><td>Scatter Packed Dword, PackedQword with Signed Dword, Signed Qword Indices</td></tr><tr><td><a href='vpscatterdd.vpscatterdq.vpscatterqd.vpscatterqq.html'>VPSCATTERQQ</a></td><td>Scatter Packed Dword, PackedQword with Signed Dword, Signed Qword Indices</td></tr><tr><td><a href='vpshld.html'>VPSHLD</a></td><td>Concatenate and Shift Packed Data Left Logical</td></tr><tr><td><a href='vpshldv.html'>VPSHLDV</a></td><td>Concatenate and Variable Shift Packed Data Left Logical</td></tr><tr><td><a href='vpshrd.html'>VPSHRD</a></td><td>Concatenate and Shift Packed Data Right Logical</td></tr><tr><td><a href='vpshrdv.html'>VPSHRDV</a></td><td>Concatenate and Variable Shift Packed Data Right Logical</td></tr><tr><td><a href='vpshufbitqmb.html'>VPSHUFBITQMB</a></td><td>Shuffle Bits From Quadword Elements Using Byte Indexes Into Mask</td></tr><tr><td><a href='vpsllvw.vpsllvd.vpsllvq.html'>VPSLLVD</a></td><td>Variable Bit Shift Left Logical</td></tr><tr><td><a href='vpsllvw.vpsllvd.vpsllvq.html'>VPSLLVQ</a></td><td>Variable Bit Shift Left Logical</td></tr><tr><td><a href='vpsllvw.vpsllvd.vpsllvq.html'>VPSLLVW</a></td><td>Variable Bit Shift Left Logical</td></tr><tr><td><a href='vpsravw.vpsravd.vpsravq.html'>VPSRAVD</a></td><td>Variable Bit Shift Right Arithmetic</td></tr><tr><td><a href='vpsravw.vpsravd.vpsravq.html'>VPSRAVQ</a></td><td>Variable Bit Shift Right Arithmetic</td></tr><tr><td><a href='vpsravw.vpsravd.vpsravq.html'>VPSRAVW</a></td><td>Variable Bit Shift Right Arithmetic</td></tr><tr><td><a href='vpsrlvw.vpsrlvd.vpsrlvq.html'>VPSRLVD</a></td><td>Variable Bit Shift Right Logical</td></tr><tr><td><a href='vpsrlvw.vpsrlvd.vpsrlvq.html'>VPSRLVQ</a></td><td>Variable Bit Shift Right Logical</td></tr><tr><td><a href='vpsrlvw.vpsrlvd.vpsrlvq.html'>VPSRLVW</a></td><td>Variable Bit Shift Right Logical</td></tr><tr><td><a href='vpternlogd.vpternlogq.html'>VPTERNLOGD</a></td><td>Bitwise Ternary Logic</td></tr><tr><td><a href='vpternlogd.vpternlogq.html'>VPTERNLOGQ</a></td><td>Bitwise Ternary Logic</td></tr><tr><td><a href='vptestmb.vptestmw.vptestmd.vptestmq.html'>VPTESTMB</a></td><td>Logical AND and Set Mask</td></tr><tr><td><a href='vptestmb.vptestmw.vptestmd.vptestmq.html'>VPTESTMD</a></td><td>Logical AND and Set Mask</td></tr><tr><td><a href='vptestmb.vptestmw.vptestmd.vptestmq.html'>VPTESTMQ</a></td><td>Logical AND and Set Mask</td></tr><tr><td><a href='vptestmb.vptestmw.vptestmd.vptestmq.html'>VPTESTMW</a></td><td>Logical AND and Set Mask</td></tr><tr><td><a href='vptestnmb.vptestnmw.vptestnmd.vptestnmq.html'>VPTESTNMB</a></td><td>Logical NAND and Set</td></tr><tr><td><a href='vptestnmb.vptestnmw.vptestnmd.vptestnmq.html'>VPTESTNMD</a></td><td>Logical NAND and Set</td></tr><tr><td><a href='vptestnmb.vptestnmw.vptestnmd.vptestnmq.html'>VPTESTNMQ</a></td><td>Logical NAND and Set</td></tr><tr><td><a href='vptestnmb.vptestnmw.vptestnmd.vptestnmq.html'>VPTESTNMW</a></td><td>Logical NAND and Set</td></tr><tr><td><a href='vrangepd.html'>VRANGEPD</a></td><td>Range Restriction Calculation for Packed Pairs of Float64 Values</td></tr><tr><td><a href='vrangeps.html'>VRANGEPS</a></td><td>Range Restriction Calculation for Packed Pairs of Float32 Values</td></tr><tr><td><a href='vrangesd.html'>VRANGESD</a></td><td>Range Restriction Calculation From a Pair of Scalar Float64 Values</td></tr><tr><td><a href='vrangess.html'>VRANGESS</a></td><td>Range Restriction Calculation From a Pair of Scalar Float32 Values</td></tr><tr><td><a href='vrcp14pd.html'>VRCP14PD</a></td><td>Compute Approximate Reciprocals of Packed Float64 Values</td></tr><tr><td><a href='vrcp14ps.html'>VRCP14PS</a></td><td>Compute Approximate Reciprocals of Packed Float32 Values</td></tr><tr><td><a href='vrcp14sd.html'>VRCP14SD</a></td><td>Compute Approximate Reciprocal of Scalar Float64 Value</td></tr><tr><td><a href='vrcp14ss.html'>VRCP14SS</a></td><td>Compute Approximate Reciprocal of Scalar Float32 Value</td></tr><tr><td><a href='vrcpph.html'>VRCPPH</a></td><td>Compute Reciprocals of Packed FP16 Values</td></tr><tr><td><a href='vrcpsh.html'>VRCPSH</a></td><td>Compute Reciprocal of Scalar FP16 Value</td></tr><tr><td><a href='vreducepd.html'>VREDUCEPD</a></td><td>Perform Reduction Transformation on Packed Float64 Values</td></tr><tr><td><a href='vreduceph.html'>VREDUCEPH</a></td><td>Perform Reduction Transformation on Packed FP16 Values</td></tr><tr><td><a href='vreduceps.html'>VREDUCEPS</a></td><td>Perform Reduction Transformation on Packed Float32 Values</td></tr><tr><td><a href='vreducesd.html'>VREDUCESD</a></td><td>Perform a Reduction Transformation on a Scalar Float64 Value</td></tr><tr><td><a href='vreducesh.html'>VREDUCESH</a></td><td>Perform Reduction Transformation on Scalar FP16 Value</td></tr><tr><td><a href='vreducess.html'>VREDUCESS</a></td><td>Perform a Reduction Transformation on a Scalar Float32 Value</td></tr><tr><td><a href='vrndscalepd.html'>VRNDSCALEPD</a></td><td>Round Packed Float64 Values to Include a Given Number of Fraction Bits</td></tr><tr><td><a href='vrndscaleph.html'>VRNDSCALEPH</a></td><td>Round Packed FP16 Values to Include a Given Number of Fraction Bits</td></tr><tr><td><a href='vrndscaleps.html'>VRNDSCALEPS</a></td><td>Round Packed Float32 Values to Include a Given Number of Fraction Bits</td></tr><tr><td><a href='vrndscalesd.html'>VRNDSCALESD</a></td><td>Round Scalar Float64 Value to Include a Given Number of Fraction Bits</td></tr><tr><td><a href='vrndscalesh.html'>VRNDSCALESH</a></td><td>Round Scalar FP16 Value to Include a Given Number of Fraction Bits</td></tr><tr><td><a href='vrndscaless.html'>VRNDSCALESS</a></td><td>Round Scalar Float32 Value to Include a Given Number of Fraction Bits</td></tr><tr><td><a href='vrsqrt14pd.html'>VRSQRT14PD</a></td><td>Compute Approximate Reciprocals of Square Roots of Packed Float64 Values</td></tr><tr><td><a href='vrsqrt14ps.html'>VRSQRT14PS</a></td><td>Compute Approximate Reciprocals of Square Roots of Packed Float32 Values</td></tr><tr><td><a href='vrsqrt14sd.html'>VRSQRT14SD</a></td><td>Compute Approximate Reciprocal of Square Root of Scalar Float64 Value</td></tr><tr><td><a href='vrsqrt14ss.html'>VRSQRT14SS</a></td><td>Compute Approximate Reciprocal of Square Root of Scalar Float32 Value</td></tr><tr><td><a href='vrsqrtph.html'>VRSQRTPH</a></td><td>Compute Reciprocals of Square Roots of Packed FP16 Values</td></tr><tr><td><a href='vrsqrtsh.html'>VRSQRTSH</a></td><td>Compute Approximate Reciprocal of Square Root of Scalar FP16 Value</td></tr><tr><td><a href='vscalefpd.html'>VSCALEFPD</a></td><td>Scale Packed Float64 Values With Float64 Values</td></tr><tr><td><a href='vscalefph.html'>VSCALEFPH</a></td><td>Scale Packed FP16 Values with FP16 Values</td></tr><tr><td><a href='vscalefps.html'>VSCALEFPS</a></td><td>Scale Packed Float32 Values With Float32 Values</td></tr><tr><td><a href='vscalefsd.html'>VSCALEFSD</a></td><td>Scale Scalar Float64 Values With Float64 Values</td></tr><tr><td><a href='vscalefsh.html'>VSCALEFSH</a></td><td>Scale Scalar FP16 Values with FP16 Values</td></tr><tr><td><a href='vscalefss.html'>VSCALEFSS</a></td><td>Scale Scalar Float32 Value With Float32 Value</td></tr><tr><td><a href='vscatterdps.vscatterdpd.vscatterqps.vscatterqpd.html'>VSCATTERDPD</a></td><td>Scatter Packed Single, PackedDouble with Signed Dword and Qword Indices</td></tr><tr><td><a href='vscatterdps.vscatterdpd.vscatterqps.vscatterqpd.html'>VSCATTERDPS</a></td><td>Scatter Packed Single, PackedDouble with Signed Dword and Qword Indices</td></tr><tr><td><a href='vscatterdps.vscatterdpd.vscatterqps.vscatterqpd.html'>VSCATTERQPD</a></td><td>Scatter Packed Single, PackedDouble with Signed Dword and Qword Indices</td></tr><tr><td><a href='vscatterdps.vscatterdpd.vscatterqps.vscatterqpd.html'>VSCATTERQPS</a></td><td>Scatter Packed Single, PackedDouble with Signed Dword and Qword Indices</td></tr><tr><td><a href='vshuff32x4.vshuff64x2.vshufi32x4.vshufi64x2.html'>VSHUFF32x4</a></td><td>Shuffle Packed Values at 128-BitGranularity</td></tr><tr><td><a href='vshuff32x4.vshuff64x2.vshufi32x4.vshufi64x2.html'>VSHUFF64x2</a></td><td>Shuffle Packed Values at 128-BitGranularity</td></tr><tr><td><a href='vshuff32x4.vshuff64x2.vshufi32x4.vshufi64x2.html'>VSHUFI32x4</a></td><td>Shuffle Packed Values at 128-BitGranularity</td></tr><tr><td><a href='vshuff32x4.vshuff64x2.vshufi32x4.vshufi64x2.html'>VSHUFI64x2</a></td><td>Shuffle Packed Values at 128-BitGranularity</td></tr><tr><td><a href='vsqrtph.html'>VSQRTPH</a></td><td>Compute Square Root of Packed FP16 Values</td></tr><tr><td><a href='vsqrtsh.html'>VSQRTSH</a></td><td>Compute Square Root of Scalar FP16 Value</td></tr><tr><td><a href='vsubph.html'>VSUBPH</a></td><td>Subtract Packed FP16 Values</td></tr><tr><td><a href='vsubsh.html'>VSUBSH</a></td><td>Subtract Scalar FP16 Value</td></tr><tr><td><a href='vtestpd.vtestps.html'>VTESTPD</a></td><td>Packed Bit Test</td></tr><tr><td><a href='vtestpd.vtestps.html'>VTESTPS</a></td><td>Packed Bit Test</td></tr><tr><td><a href='vucomish.html'>VUCOMISH</a></td><td>Unordered Compare Scalar FP16 Values and Set EFLAGS</td></tr><tr><td><a href='vzeroall.html'>VZEROALL</a></td><td>Zero XMM, YMM, and ZMM Registers</td></tr><tr><td><a href='vzeroupper.html'>VZEROUPPER</a></td><td>Zero Upper Bits of YMM and ZMM Registers</td></tr><tr><td><a href='wait.fwait.html'>WAIT</a></td><td>Wait</td></tr><tr><td><a href='wbinvd.html'>WBINVD</a></td><td>Write Back and Invalidate Cache</td></tr><tr><td><a href='wbnoinvd.html'>WBNOINVD</a></td><td>Write Back and Do Not Invalidate Cache</td></tr><tr><td><a href='wrfsbase.wrgsbase.html'>WRFSBASE</a></td><td>Write FS/GS Segment Base</td></tr><tr><td><a href='wrfsbase.wrgsbase.html'>WRGSBASE</a></td><td>Write FS/GS Segment Base</td></tr><tr><td><a href='wrmsr.html'>WRMSR</a></td><td>Write to Model Specific Register</td></tr><tr><td><a href='wrpkru.html'>WRPKRU</a></td><td>Write Data to User Page Key Register</td></tr><tr><td><a href='wrssd.wrssq.html'>WRSSD</a></td><td>Write to Shadow Stack</td></tr><tr><td><a href='wrssd.wrssq.html'>WRSSQ</a></td><td>Write to Shadow Stack</td></tr><tr><td><a href='wrussd.wrussq.html'>WRUSSD</a></td><td>Write to User Shadow Stack</td></tr><tr><td><a href='wrussd.wrussq.html'>WRUSSQ</a></td><td>Write to User Shadow Stack</td></tr><tr><td><a href='xabort.html'>XABORT</a></td><td>Transactional Abort</td></tr><tr><td><a href='xacquire.xrelease.html'>XACQUIRE</a></td><td>Hardware Lock Elision Prefix Hints</td></tr><tr><td><a href='xadd.html'>XADD</a></td><td>Exchange and Add</td></tr><tr><td><a href='xbegin.html'>XBEGIN</a></td><td>Transactional Begin</td></tr><tr><td><a href='xchg.html'>XCHG</a></td><td>Exchange Register/Memory With Register</td></tr><tr><td><a href='xend.html'>XEND</a></td><td>Transactional End</td></tr><tr><td><a href='xgetbv.html'>XGETBV</a></td><td>Get Value of Extended Control Register</td></tr><tr><td><a href='xlat.xlatb.html'>XLAT</a></td><td>Table Look-up Translation</td></tr><tr><td><a href='xlat.xlatb.html'>XLATB</a></td><td>Table Look-up Translation</td></tr><tr><td><a href='xor.html'>XOR</a></td><td>Logical Exclusive OR</td></tr><tr><td><a href='xorpd.html'>XORPD</a></td><td>Bitwise Logical XOR of Packed Double Precision Floating-Point Values</td></tr><tr><td><a href='xorps.html'>XORPS</a></td><td>Bitwise Logical XOR of Packed Single Precision Floating-Point Values</td></tr><tr><td><a href='xacquire.xrelease.html'>XRELEASE</a></td><td>Hardware Lock Elision Prefix Hints</td></tr><tr><td><a href='xresldtrk.html'>XRESLDTRK</a></td><td>Resume Tracking Load Addresses</td></tr><tr><td><a href='xrstor.html'>XRSTOR</a></td><td>Restore Processor Extended States</td></tr><tr><td><a href='xrstors.html'>XRSTORS</a></td><td>Restore Processor Extended States Supervisor</td></tr><tr><td><a href='xsave.html'>XSAVE</a></td><td>Save Processor Extended States</td></tr><tr><td><a href='xsavec.html'>XSAVEC</a></td><td>Save Processor Extended States With Compaction</td></tr><tr><td><a href='xsaveopt.html'>XSAVEOPT</a></td><td>Save Processor Extended States Optimized</td></tr><tr><td><a href='xsaves.html'>XSAVES</a></td><td>Save Processor Extended States Supervisor</td></tr><tr><td><a href='xsetbv.html'>XSETBV</a></td><td>Set Extended Control Register</td></tr><tr><td><a href='xsusldtrk.html'>XSUSLDTRK</a></td><td>Suspend Tracking Load Addresses</td></tr><tr><td><a href='xtest.html'>XTEST</a></td><td>Test if in Transactional Execution</td></tr></table><h2>SGX Instructions</h2><table><tr><th>Mnemonic</th><th>Summary</th></tr><tr><td><a href='encls.html'>ENCLS</a></td><td>Execute an Enclave System Function of Specified Leaf Number</td></tr><tr><td><a href='eadd.html'>ENCLS[EADD]</a></td><td>Add a Page to an Uninitialized Enclave</td></tr><tr><td><a href='eaug.html'>ENCLS[EAUG]</a></td><td>Add a Page to an Initialized Enclave</td></tr><tr><td><a href='eblock.html'>ENCLS[EBLOCK]</a></td><td>Mark a page in EPC as Blocked</td></tr><tr><td><a href='ecreate.html'>ENCLS[ECREATE]</a></td><td>Create an SECS page in the Enclave Page Cache</td></tr><tr><td><a href='edbgrd.html'>ENCLS[EDBGRD]</a></td><td>Read From a Debug Enclave</td></tr><tr><td><a href='edbgwr.html'>ENCLS[EDBGWR]</a></td><td>Write to a Debug Enclave</td></tr><tr><td><a href='eextend.html'>ENCLS[EEXTEND]</a></td><td>Extend Uninitialized Enclave Measurement by 256 Bytes</td></tr><tr><td><a href='einit.html'>ENCLS[EINIT]</a></td><td>Initialize an Enclave for Execution</td></tr><tr><td><a href='eldb.eldu.eldbc.elduc.html'>ENCLS[ELDBC]</a></td><td>Load an EPC Page and Mark its State</td></tr><tr><td><a href='eldb.eldu.eldbc.elduc.html'>ENCLS[ELDB]</a></td><td>Load an EPC Page and Mark its State</td></tr><tr><td><a href='eldb.eldu.eldbc.elduc.html'>ENCLS[ELDUC]</a></td><td>Load an EPC Page and Mark its State</td></tr><tr><td><a href='eldb.eldu.eldbc.elduc.html'>ENCLS[ELDU]</a></td><td>Load an EPC Page and Mark its State</td></tr><tr><td><a href='emodpr.html'>ENCLS[EMODPR]</a></td><td>Restrict the Permissions of an EPC Page</td></tr><tr><td><a href='emodt.html'>ENCLS[EMODT]</a></td><td>Change the Type of an EPC Page</td></tr><tr><td><a href='epa.html'>ENCLS[EPA]</a></td><td>Add Version Array</td></tr><tr><td><a href='erdinfo.html'>ENCLS[ERDINFO]</a></td><td>Read Type and Status Information About an EPC Page</td></tr><tr><td><a href='eremove.html'>ENCLS[EREMOVE]</a></td><td>Remove a page from the EPC</td></tr><tr><td><a href='etrackc.html'>ENCLS[ETRACKC]</a></td><td>Activates EBLOCK Checks</td></tr><tr><td><a href='etrack.html'>ENCLS[ETRACK]</a></td><td>Activates EBLOCK Checks</td></tr><tr><td><a href='ewb.html'>ENCLS[EWB]</a></td><td>Invalidate an EPC Page and Write out to Main Memory</td></tr><tr><td><a href='enclu.html'>ENCLU</a></td><td>Execute an Enclave User Function of Specified Leaf Number</td></tr><tr><td><a href='eacceptcopy.html'>ENCLU[EACCEPTCOPY]</a></td><td>Initialize a Pending Page</td></tr><tr><td><a href='eaccept.html'>ENCLU[EACCEPT]</a></td><td>Accept Changes to an EPC Page</td></tr><tr><td><a href='edeccssa.html'>ENCLU[EDECCSSA]</a></td><td>Decrements TCS.CSSA</td></tr><tr><td><a href='eenter.html'>ENCLU[EENTER]</a></td><td>Enters an Enclave</td></tr><tr><td><a href='eexit.html'>ENCLU[EEXIT]</a></td><td>Exits an Enclave</td></tr><tr><td><a href='egetkey.html'>ENCLU[EGETKEY]</a></td><td>Retrieves a Cryptographic Key</td></tr><tr><td><a href='emodpe.html'>ENCLU[EMODPE]</a></td><td>Extend an EPC Page Permissions</td></tr><tr><td><a href='ereport.html'>ENCLU[EREPORT]</a></td><td>Create a Cryptographic Report of the Enclave</td></tr><tr><td><a href='eresume.html'>ENCLU[ERESUME]</a></td><td>Re-Enters an Enclave</td></tr><tr><td><a href='enclv.html'>ENCLV</a></td><td>Execute an Enclave VMM Function of Specified Leaf Number</td></tr><tr><td><a href='edecvirtchild.html'>ENCLV[EDECVIRTCHILD]</a></td><td>Decrement VIRTCHILDCNT in SECS</td></tr><tr><td><a href='eincvirtchild.html'>ENCLV[EINCVIRTCHILD]</a></td><td>Increment VIRTCHILDCNT in SECS</td></tr><tr><td><a href='esetcontext.html'>ENCLV[ESETCONTEXT]</a></td><td>Set the ENCLAVECONTEXT Field in SECS</td></tr></table><h2>SMX Instructions</h2><table><tr><th>Mnemonic</th><th>Summary</th></tr><tr><td><a href='capabilities.html'>GETSEC[CAPABILITIES]</a></td><td>Report the SMX Capabilities</td></tr><tr><td><a href='enteraccs.html'>GETSEC[ENTERACCS]</a></td><td>Execute Authenticated Chipset Code</td></tr><tr><td><a href='exitac.html'>GETSEC[EXITAC]</a></td><td>Exit Authenticated Code Execution Mode</td></tr><tr><td><a href='parameters.html'>GETSEC[PARAMETERS]</a></td><td>Report the SMX Parameters</td></tr><tr><td><a href='senter.html'>GETSEC[SENTER]</a></td><td>Enter a Measured Environment</td></tr><tr><td><a href='sexit.html'>GETSEC[SEXIT]</a></td><td>Exit Measured Environment</td></tr><tr><td><a href='smctrl.html'>GETSEC[SMCTRL]</a></td><td>SMX Mode Control</td></tr><tr><td><a href='wakeup.html'>GETSEC[WAKEUP]</a></td><td>Wake Up Sleeping Processors in Measured Environment</td></tr></table><h2>VMX Instructions</h2><table><tr><th>Mnemonic</th><th>Summary</th></tr><tr><td><a href='invept.html'>INVEPT</a></td><td>Invalidate Translations Derived from EPT</td></tr><tr><td><a href='invvpid.html'>INVVPID</a></td><td>Invalidate Translations Based on VPID</td></tr><tr><td><a href='vmcall.html'>VMCALL</a></td><td>Call to VM Monitor</td></tr><tr><td><a href='vmclear.html'>VMCLEAR</a></td><td>Clear Virtual-Machine Control Structure</td></tr><tr><td><a href='vmfunc.html'>VMFUNC</a></td><td>Invoke VM function</td></tr><tr><td><a href='vmlaunch.vmresume.html'>VMLAUNCH</a></td><td>Launch/Resume Virtual Machine</td></tr><tr><td><a href='vmptrld.html'>VMPTRLD</a></td><td>Load Pointer to Virtual-Machine Control Structure</td></tr><tr><td><a href='vmptrst.html'>VMPTRST</a></td><td>Store Pointer to Virtual-Machine Control Structure</td></tr><tr><td><a href='vmread.html'>VMREAD</a></td><td>Read Field from Virtual-Machine Control Structure</td></tr><tr><td><a href='vmlaunch.vmresume.html'>VMRESUME</a></td><td>Launch/Resume Virtual Machine</td></tr><tr><td><a href='vmresume.html'>VMRESUME</a> (1)</td><td>Resume Virtual Machine</td></tr><tr><td><a href='vmwrite.html'>VMWRITE</a></td><td>Write Field to Virtual-Machine Control Structure</td></tr><tr><td><a href='vmxoff.html'>VMXOFF</a></td><td>Leave VMX Operation</td></tr><tr><td><a href='vmxon.html'>VMXON</a></td><td>Enter VMX Operation</td></tr></table><h2>Xeon Phi™ Instructions</h2><table><tr><th>Mnemonic</th><th>Summary</th></tr><tr><td><a href='prefetchwt1.html'>PREFETCHWT1</a></td><td>Prefetch Vector Data Into Caches With Intent to Write and T1 Hint</td></tr><tr><td><a href='v4fmaddps.v4fnmaddps.html'>V4FMADDPS</a></td><td>Packed Single Precision Floating-Point Fused Multiply-Add(4-Iterations)</td></tr><tr><td><a href='v4fmaddss.v4fnmaddss.html'>V4FMADDSS</a></td><td>Scalar Single Precision Floating-Point Fused Multiply-Add(4-Iterations)</td></tr><tr><td><a href='v4fmaddps.v4fnmaddps.html'>V4FNMADDPS</a></td><td>Packed Single Precision Floating-Point Fused Multiply-Add(4-Iterations)</td></tr><tr><td><a href='v4fmaddss.v4fnmaddss.html'>V4FNMADDSS</a></td><td>Scalar Single Precision Floating-Point Fused Multiply-Add(4-Iterations)</td></tr><tr><td><a href='vexp2pd.html'>VEXP2PD</a></td><td>Approximation to the Exponential 2^x of Packed Double Precision Floating-PointValues With Less Than 2^-23 Relative Error</td></tr><tr><td><a href='vexp2ps.html'>VEXP2PS</a></td><td>Approximation to the Exponential 2^x of Packed Single Precision Floating-PointValues With Less Than 2^-23 Relative Error</td></tr><tr><td><a href='vgatherpf0dps.vgatherpf0qps.vgatherpf0dpd.vgatherpf0qpd.html'>VGATHERPF0DPD</a></td><td>Sparse PrefetchPacked SP/DP Data Values With Signed Dword, Signed Qword Indices Using T0 Hint</td></tr><tr><td><a href='vgatherpf0dps.vgatherpf0qps.vgatherpf0dpd.vgatherpf0qpd.html'>VGATHERPF0DPS</a></td><td>Sparse PrefetchPacked SP/DP Data Values With Signed Dword, Signed Qword Indices Using T0 Hint</td></tr><tr><td><a href='vgatherpf0dps.vgatherpf0qps.vgatherpf0dpd.vgatherpf0qpd.html'>VGATHERPF0QPD</a></td><td>Sparse PrefetchPacked SP/DP Data Values With Signed Dword, Signed Qword Indices Using T0 Hint</td></tr><tr><td><a href='vgatherpf0dps.vgatherpf0qps.vgatherpf0dpd.vgatherpf0qpd.html'>VGATHERPF0QPS</a></td><td>Sparse PrefetchPacked SP/DP Data Values With Signed Dword, Signed Qword Indices Using T0 Hint</td></tr><tr><td><a href='vgatherpf1dps.vgatherpf1qps.vgatherpf1dpd.vgatherpf1qpd.html'>VGATHERPF1DPD</a></td><td>Sparse PrefetchPacked SP/DP Data Values With Signed Dword, Signed Qword Indices Using T1 Hint</td></tr><tr><td><a href='vgatherpf1dps.vgatherpf1qps.vgatherpf1dpd.vgatherpf1qpd.html'>VGATHERPF1DPS</a></td><td>Sparse PrefetchPacked SP/DP Data Values With Signed Dword, Signed Qword Indices Using T1 Hint</td></tr><tr><td><a href='vgatherpf1dps.vgatherpf1qps.vgatherpf1dpd.vgatherpf1qpd.html'>VGATHERPF1QPD</a></td><td>Sparse PrefetchPacked SP/DP Data Values With Signed Dword, Signed Qword Indices Using T1 Hint</td></tr><tr><td><a href='vgatherpf1dps.vgatherpf1qps.vgatherpf1dpd.vgatherpf1qpd.html'>VGATHERPF1QPS</a></td><td>Sparse PrefetchPacked SP/DP Data Values With Signed Dword, Signed Qword Indices Using T1 Hint</td></tr><tr><td><a href='vp4dpwssd.html'>VP4DPWSSD</a></td><td>Dot Product of Signed Words With Dword Accumulation (4-Iterations)</td></tr><tr><td><a href='vp4dpwssds.html'>VP4DPWSSDS</a></td><td>Dot Product of Signed Words With Dword Accumulation and Saturation(4-Iterations)</td></tr><tr><td><a href='vrcp28pd.html'>VRCP28PD</a></td><td>Approximation to the Reciprocal of Packed Double Precision Floating-Point ValuesWith Less Than 2^-28 Relative Error</td></tr><tr><td><a href='vrcp28ps.html'>VRCP28PS</a></td><td>Approximation to the Reciprocal of Packed Single Precision Floating-Point ValuesWith Less Than 2^-28 Relative Error</td></tr><tr><td><a href='vrcp28sd.html'>VRCP28SD</a></td><td>Approximation to the Reciprocal of Scalar Double Precision Floating-Point ValueWith Less Than 2^-28 Relative Error</td></tr><tr><td><a href='vrcp28ss.html'>VRCP28SS</a></td><td>Approximation to the Reciprocal of Scalar Single Precision Floating-Point ValueWith Less Than 2^-28 Relative Error</td></tr><tr><td><a href='vrsqrt28pd.html'>VRSQRT28PD</a></td><td>Approximation to the Reciprocal Square Root of Packed Double PrecisionFloating-Point Values With Less Than 2^-28 Relative Error</td></tr><tr><td><a href='vrsqrt28ps.html'>VRSQRT28PS</a></td><td>Approximation to the Reciprocal Square Root of Packed Single PrecisionFloating-Point Values With Less Than 2^-28 Relative Error</td></tr><tr><td><a href='vrsqrt28sd.html'>VRSQRT28SD</a></td><td>Approximation to the Reciprocal Square Root of Scalar Double PrecisionFloating-Point Value With Less Than 2^-28 Relative Error</td></tr><tr><td><a href='vrsqrt28ss.html'>VRSQRT28SS</a></td><td>Approximation to the Reciprocal Square Root of Scalar Single Precision Floating-Point Value With Less Than 2^-28 Relative Error</td></tr><tr><td><a href='vscatterpf0dps.vscatterpf0qps.vscatterpf0dpd.vscatterpf0qpd.html'>VSCATTERPF0DPD</a></td><td>Sparse PrefetchPacked SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint With Intentto Write</td></tr><tr><td><a href='vscatterpf0dps.vscatterpf0qps.vscatterpf0dpd.vscatterpf0qpd.html'>VSCATTERPF0DPS</a></td><td>Sparse PrefetchPacked SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint With Intentto Write</td></tr><tr><td><a href='vscatterpf0dps.vscatterpf0qps.vscatterpf0dpd.vscatterpf0qpd.html'>VSCATTERPF0QPD</a></td><td>Sparse PrefetchPacked SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint With Intentto Write</td></tr><tr><td><a href='vscatterpf0dps.vscatterpf0qps.vscatterpf0dpd.vscatterpf0qpd.html'>VSCATTERPF0QPS</a></td><td>Sparse PrefetchPacked SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint With Intentto Write</td></tr><tr><td><a href='vscatterpf1dps.vscatterpf1qps.vscatterpf1dpd.vscatterpf1qpd.html'>VSCATTERPF1DPD</a></td><td>Sparse PrefetchPacked SP/DP Data Values With Signed Dword, Signed Qword Indices Using T1 Hint With Intentto Write</td></tr><tr><td><a href='vscatterpf1dps.vscatterpf1qps.vscatterpf1dpd.vscatterpf1qpd.html'>VSCATTERPF1DPS</a></td><td>Sparse PrefetchPacked SP/DP Data Values With Signed Dword, Signed Qword Indices Using T1 Hint With Intentto Write</td></tr><tr><td><a href='vscatterpf1dps.vscatterpf1qps.vscatterpf1dpd.vscatterpf1qpd.html'>VSCATTERPF1QPD</a></td><td>Sparse PrefetchPacked SP/DP Data Values With Signed Dword, Signed Qword Indices Using T1 Hint With Intentto Write</td></tr><tr><td><a href='vscatterpf1dps.vscatterpf1qps.vscatterpf1dpd.vscatterpf1qpd.html'>VSCATTERPF1QPS</a></td><td>Sparse PrefetchPacked SP/DP Data Values With Signed Dword, Signed Qword Indices Using T1 Hint With Intentto Write</td></tr></table><footer><p>
This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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