forked from NRZCode/ia32-64
10 lines
138 KiB
HTML
10 lines
138 KiB
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>x86 and amd64 instruction reference</title></head><body><h1>x86 and amd64 instruction reference</h1><p>Derived from the December 2023 version of the <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a>. Last updated 2024-02-18.</p><p><strong>THIS REFERENCE IS NOT PERFECT.</strong> It's been mechanically separated into distinct files by a
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dumb script. It may be enough to replace the official documentation on your weekend reverse engineering
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project, but for anything where money is at stake, go get the official and freely available documentation.
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</p><h2>Core Instructions</h2><table><tr><th>Mnemonic</th><th>Summary</th></tr><tr><td><a href='aaa.html'>AAA</a></td><td>ASCII Adjust After Addition</td></tr><tr><td><a href='aad.html'>AAD</a></td><td>ASCII Adjust AX Before Division</td></tr><tr><td><a href='aam.html'>AAM</a></td><td>ASCII Adjust AX After Multiply</td></tr><tr><td><a href='aas.html'>AAS</a></td><td>ASCII Adjust AL After Subtraction</td></tr><tr><td><a href='adc.html'>ADC</a></td><td>Add With Carry</td></tr><tr><td><a href='adcx.html'>ADCX</a></td><td>Unsigned Integer Addition of Two Operands With Carry Flag</td></tr><tr><td><a href='add.html'>ADD</a></td><td>Add</td></tr><tr><td><a href='addpd.html'>ADDPD</a></td><td>Add Packed Double Precision Floating-Point Values</td></tr><tr><td><a href='addps.html'>ADDPS</a></td><td>Add Packed Single Precision Floating-Point Values</td></tr><tr><td><a href='addsd.html'>ADDSD</a></td><td>Add Scalar Double Precision Floating-Point Values</td></tr><tr><td><a href='addss.html'>ADDSS</a></td><td>Add Scalar Single Precision Floating-Point Values</td></tr><tr><td><a href='addsubpd.html'>ADDSUBPD</a></td><td>Packed Double Precision Floating-Point Add/Subtract</td></tr><tr><td><a href='addsubps.html'>ADDSUBPS</a></td><td>Packed Single Precision Floating-Point Add/Subtract</td></tr><tr><td><a href='adox.html'>ADOX</a></td><td>Unsigned Integer Addition of Two Operands With Overflow Flag</td></tr><tr><td><a href='aesdec.html'>AESDEC</a></td><td>Perform One Round of an AES Decryption Flow</td></tr><tr><td><a href='aesdec128kl.html'>AESDEC128KL</a></td><td>Perform Ten Rounds of AES Decryption Flow With Key Locker Using 128-BitKey</td></tr><tr><td><a href='aesdec256kl.html'>AESDEC256KL</a></td><td>Perform 14 Rounds of AES Decryption Flow With Key Locker Using 256-Bit Key</td></tr><tr><td><a href='aesdeclast.html'>AESDECLAST</a></td><td>Perform Last Round of an AES Decryption Flow</td></tr><tr><td><a href='aesdecwide128kl.html'>AESDECWIDE128KL</a></td><td>Perform Ten Rounds of AES Decryption Flow With Key Locker on 8 BlocksUsing 128-Bit Key</td></tr><tr><td><a href='aesdecwide256kl.html'>AESDECWIDE256KL</a></td><td>Perform 14 Rounds of AES Decryption Flow With Key Locker on 8 BlocksUsing 256-Bit Key</td></tr><tr><td><a href='aesenc.html'>AESENC</a></td><td>Perform One Round of an AES Encryption Flow</td></tr><tr><td><a href='aesenc128kl.html'>AESENC128KL</a></td><td>Perform Ten Rounds of AES Encryption Flow With Key Locker Using 128-Bit Key</td></tr><tr><td><a href='aesenc256kl.html'>AESENC256KL</a></td><td>Perform 14 Rounds of AES Encryption Flow With Key Locker Using 256-Bit Key</td></tr><tr><td><a href='aesenclast.html'>AESENCLAST</a></td><td>Perform Last Round of an AES Encryption Flow</td></tr><tr><td><a href='aesencwide128kl.html'>AESENCWIDE128KL</a></td><td>Perform Ten Rounds of AES Encryption Flow With Key Locker on 8 BlocksUsing 128-Bit Key</td></tr><tr><td><a href='aesencwide256kl.html'>AESENCWIDE256KL</a></td><td>Perform 14 Rounds of AES Encryption Flow With Key Locker on 8 BlocksUsing 256-Bit Key</td></tr><tr><td><a href='aesimc.html'>AESIMC</a></td><td>Perform the AES InvMixColumn Transformation</td></tr><tr><td><a href='aeskeygenassist.html'>AESKEYGENASSIST</a></td><td>AES Round Key Generation Assist</td></tr><tr><td><a href='and.html'>AND</a></td><td>Logical AND</td></tr><tr><td><a href='andn.html'>ANDN</a></td><td>Logical AND NOT</td></tr><tr><td><a href='andnpd.html'>ANDNPD</a></td><td>Bitwise Logical AND NOT of Packed Double Precision Floating-Point Values</td></tr><tr><td><a href='andnps.html'>ANDNPS</a></td><td>Bitwise Logical AND NOT of Packed Single Precision Floating-Point Values</td></tr><tr><td><a href='andpd.html'>ANDPD</a></td><td>Bitwise Logical AND of Packed Double Precision Floating-Point Values</td></tr><tr><td><a href='andps.html'>ANDPS</a></td><td>Bitwise Logical AND of Packed Single Precision Floating-Point Values</td></tr><tr><td><a href='arpl.html'>ARPL</a></td><td>Adjust RPL Field of Segment Selector</td></tr><tr><td><a href='bextr.html'>BEXTR</a></td><td>Bit Field Extract</td></tr><tr><td>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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