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5.1 KiB
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107 lines
5.1 KiB
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>VPBLENDD
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— Blend Packed Dwords</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>VPBLENDD
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— Blend Packed Dwords</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32 -bit Mode</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>VEX.128.66.0F3A.W0 02 /r ib VPBLENDD xmm1, xmm2, xmm3/m128, imm8</td>
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<td>RVMI</td>
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<td>V/V</td>
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<td>AVX2</td>
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<td>Select dwords from xmm2 and xmm3/m128 from mask specified in imm8 and store the values into xmm1.</td></tr>
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<tr>
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<td>VEX.256.66.0F3A.W0 02 /r ib VPBLENDD ymm1, ymm2, ymm3/m256, imm8</td>
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<td>RVMI</td>
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<td>V/V</td>
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<td>AVX2</td>
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<td>Select dwords from ymm2 and ymm3/m256 from mask specified in imm8 and store the values into ymm1.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>RVMI</td>
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<td>ModRM:reg (w)</td>
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<td>VEX.vvvv (r)</td>
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<td>ModRM:r/m (r)</td>
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<td>imm8</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Dword elements from the source operand (second operand) are conditionally written to the destination operand (first operand) depending on bits in the immediate operand (third operand). The immediate bits (bits 7:0) form a mask that determines whether the corresponding dword in the destination is copied from the source. If a bit in the mask, corresponding to a dword, is “1", then the dword is copied, else the dword is unchanged.</p>
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<p>VEX.128 encoded version: The second source operand can be an XMM register or a 128-bit memory location. The first source and destination operands are XMM registers. Bits (MAXVL-1:128) of the corresponding YMM register are zeroed.</p>
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<p>VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register or a 256-bit memory location. The destination operand is a YMM register.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<h3 id="vpblendd--vex-256-encoded-version-">VPBLENDD (VEX.256 encoded version)<a class="anchor" href="#vpblendd--vex-256-encoded-version-">
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¶
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</a></h3>
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<pre>IF (imm8[0] == 1) THEN DEST[31:0] := SRC2[31:0]
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ELSE DEST[31:0] := SRC1[31:0]
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IF (imm8[1] == 1) THEN DEST[63:32] := SRC2[63:32]
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ELSE DEST[63:32] := SRC1[63:32]
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IF (imm8[2] == 1) THEN DEST[95:64] := SRC2[95:64]
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ELSE DEST[95:64] := SRC1[95:64]
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IF (imm8[3] == 1) THEN DEST[127:96] := SRC2[127:96]
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ELSE DEST[127:96] := SRC1[127:96]
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IF (imm8[4] == 1) THEN DEST[159:128] := SRC2[159:128]
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ELSE DEST[159:128] := SRC1[159:128]
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IF (imm8[5] == 1) THEN DEST[191:160] := SRC2[191:160]
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ELSE DEST[191:160] := SRC1[191:160]
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IF (imm8[6] == 1) THEN DEST[223:192] := SRC2[223:192]
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ELSE DEST[223:192] := SRC1[223:192]
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IF (imm8[7] == 1) THEN DEST[255:224] := SRC2[255:224]
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ELSE DEST[255:224] := SRC1[255:224]
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</pre>
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<h3 id="vpblendd--vex-128-encoded-version-">VPBLENDD (VEX.128 encoded version)<a class="anchor" href="#vpblendd--vex-128-encoded-version-">
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¶
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</a></h3>
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<pre>IF (imm8[0] == 1) THEN DEST[31:0] := SRC2[31:0]
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ELSE DEST[31:0] := SRC1[31:0]
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IF (imm8[1] == 1) THEN DEST[63:32] := SRC2[63:32]
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ELSE DEST[63:32] := SRC1[63:32]
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IF (imm8[2] == 1) THEN DEST[95:64] := SRC2[95:64]
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ELSE DEST[95:64] := SRC1[95:64]
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IF (imm8[3] == 1) THEN DEST[127:96] := SRC2[127:96]
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ELSE DEST[127:96] := SRC1[127:96]
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DEST[MAXVL-1:128] := 0
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</pre>
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<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h2>
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<pre>VPBLENDD: __m128i _mm_blend_epi32 (__m128i v1, __m128i v2, const int mask)
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</pre>
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<pre>VPBLENDD: __m256i _mm256_blend_epi32 (__m256i v1, __m256i v2, const int mask)
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</pre>
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<h2 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h2>
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<p>See <span class="not-imported">Table 2-21</span>, “Type 4 Class Exception Conditions.”</p>
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<p>Additionally:</p>
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<table>
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<tr>
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<td>#UD</td>
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<td>If VEX.W = 1.</td></tr></table><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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