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<!DOCTYPE html>
<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M
— Convert a Vector Register to a Mask</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M
— Convert a Vector Register to a Mask</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op/En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>EVEX.128.F3.0F38.W0 29 /r VPMOVB2M k1, xmm1</td>
<td>RM</td>
<td>V/V</td>
<td>AVX512VL AVX512BW</td>
<td>Sets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding byte in XMM1.</td></tr>
<tr>
<td>EVEX.256.F3.0F38.W0 29 /r VPMOVB2M k1, ymm1</td>
<td>RM</td>
<td>V/V</td>
<td>AVX512VL AVX512BW</td>
<td>Sets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding byte in YMM1.</td></tr>
<tr>
<td>EVEX.512.F3.0F38.W0 29 /r VPMOVB2M k1, zmm1</td>
<td>RM</td>
<td>V/V</td>
<td>AVX512BW</td>
<td>Sets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding byte in ZMM1.</td></tr>
<tr>
<td>EVEX.128.F3.0F38.W1 29 /r VPMOVW2M k1, xmm1</td>
<td>RM</td>
<td>V/V</td>
<td>AVX512VL AVX512BW</td>
<td>Sets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding word in XMM1.</td></tr>
<tr>
<td>EVEX.256.F3.0F38.W1 29 /r VPMOVW2M k1, ymm1</td>
<td>RM</td>
<td>V/V</td>
<td>AVX512VL AVX512BW</td>
<td>Sets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding word in YMM1.</td></tr>
<tr>
<td>EVEX.512.F3.0F38.W1 29 /r VPMOVW2M k1, zmm1</td>
<td>RM</td>
<td>V/V</td>
<td>AVX512BW</td>
<td>Sets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding word in ZMM1.</td></tr>
<tr>
<td>EVEX.128.F3.0F38.W0 39 /r VPMOVD2M k1, xmm1</td>
<td>RM</td>
<td>V/V</td>
<td>AVX512VL AVX512DQ</td>
<td>Sets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding doubleword in XMM1.</td></tr>
<tr>
<td>EVEX.256.F3.0F38.W0 39 /r VPMOVD2M k1, ymm1</td>
<td>RM</td>
<td>V/V</td>
<td>AVX512VL AVX512DQ</td>
<td>Sets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding doubleword in YMM1.</td></tr>
<tr>
<td>EVEX.512.F3.0F38.W0 39 /r VPMOVD2M k1, zmm1</td>
<td>RM</td>
<td>V/V</td>
<td>AVX512DQ</td>
<td>Sets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding doubleword in ZMM1.</td></tr>
<tr>
<td>EVEX.128.F3.0F38.W1 39 /r VPMOVQ2M k1, xmm1</td>
<td>RM</td>
<td>V/V</td>
<td>AVX512VL AVX512DQ</td>
<td>Sets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding quadword in XMM1.</td></tr>
<tr>
<td>EVEX.256.F3.0F38.W1 39 /r VPMOVQ2M k1, ymm1</td>
<td>RM</td>
<td>V/V</td>
<td>AVX512VL AVX512DQ</td>
<td>Sets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding quadword in YMM1.</td></tr>
<tr>
<td>EVEX.512.F3.0F38.W1 39 /r VPMOVQ2M k1, zmm1</td>
<td>RM</td>
<td>V/V</td>
<td>AVX512DQ</td>
<td>Sets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding quadword in ZMM1.</td></tr></table>
<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
</a></h2>
<table>
<tr>
<th>Op/En</th>
<th>Operand 1</th>
<th>Operand 2</th>
<th>Operand 3</th>
<th>Operand 4</th></tr>
<tr>
<td>RM</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>N/A</td>
<td>N/A</td></tr></table>
<h3 id="description">Description<a class="anchor" href="#description">
</a></h3>
<p>Converts a vector register to a mask register. Each element in the destination register is set to 1 or 0 depending on the value of most significant bit of the corresponding element in the source register.</p>
<p>The source operand is a ZMM/YMM/XMM register. The destination operand is a mask register.</p>
<p>EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.</p>
<h3 id="operation">Operation<a class="anchor" href="#operation">
</a></h3>
<h4 id="vpmovb2m--evex-encoded-versions-">VPMOVB2M (EVEX encoded versions)<a class="anchor" href="#vpmovb2m--evex-encoded-versions-">
</a></h4>
<pre>(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j := 0 TO KL-1
i := j * 8
IF SRC[i+7]
THEN DEST[j]:=1
ELSE DEST[j] := 0
FI;
ENDFOR
DEST[MAX_KL-1:KL] := 0
</pre>
<h4 id="vpmovw2m--evex-encoded-versions-">VPMOVW2M (EVEX encoded versions)<a class="anchor" href="#vpmovw2m--evex-encoded-versions-">
</a></h4>
<pre>(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO KL-1
i := j * 16
IF SRC[i+15]
THEN DEST[j]:=1
ELSE DEST[j] := 0
FI;
ENDFOR
DEST[MAX_KL-1:KL] := 0
</pre>
<h4 id="vpmovd2m--evex-encoded-versions-">VPMOVD2M (EVEX encoded versions)<a class="anchor" href="#vpmovd2m--evex-encoded-versions-">
</a></h4>
<pre>(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF SRC[i+31]
THEN DEST[j]:=1
ELSE DEST[j] := 0
FI;
ENDFOR
DEST[MAX_KL-1:KL] := 0
</pre>
<h4 id="vpmovq2m--evex-encoded-versions-">VPMOVQ2M (EVEX encoded versions)<a class="anchor" href="#vpmovq2m--evex-encoded-versions-">
</a></h4>
<pre>(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF SRC[i+63]
THEN DEST[j]:=1
ELSE DEST[j] := 0
FI;
ENDFOR
DEST[MAX_KL-1:KL] := 0
</pre>
<h3 id="intel-c-c++-compiler-intrinsic-equivalents">Intel C/C++ Compiler Intrinsic Equivalents<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalents">
</a></h3>
<pre>VPMPOVB2M __mmask64 _mm512_movepi8_mask( __m512i );
</pre>
<pre>VPMPOVD2M __mmask16 _mm512_movepi32_mask( __m512i );
</pre>
<pre>VPMPOVQ2M __mmask8 _mm512_movepi64_mask( __m512i );
</pre>
<pre>VPMPOVW2M __mmask32 _mm512_movepi16_mask( __m512i );
</pre>
<pre>VPMPOVB2M __mmask32 _mm256_movepi8_mask( __m256i );
</pre>
<pre>VPMPOVD2M __mmask8 _mm256_movepi32_mask( __m256i );
</pre>
<pre>VPMPOVQ2M __mmask8 _mm256_movepi64_mask( __m256i );
</pre>
<pre>VPMPOVW2M __mmask16 _mm256_movepi16_mask( __m256i );
</pre>
<pre>VPMPOVB2M __mmask16 _mm_movepi8_mask( __m128i );
</pre>
<pre>VPMPOVD2M __mmask8 _mm_movepi32_mask( __m128i );
</pre>
<pre>VPMPOVQ2M __mmask8 _mm_movepi64_mask( __m128i );
</pre>
<pre>VPMPOVW2M __mmask8 _mm_movepi16_mask( __m128i );
</pre>
<h3 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
</a></h3>
<p>None.</p>
<h3 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
</a></h3>
<p>EVEX-encoded instruction, see <span class="not-imported">Table 2-55</span>, “Type E7NM Class Exception Conditions.”</p>
<p>Additionally:</p>
<table>
<tr>
<td>#UD</td>
<td>If EVEX.vvvv != 1111B.</td></tr></table><footer><p>
This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
</p></footer></body></html>
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