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<!DOCTYPE html>
<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>VPERMILPS
— Permute In-Lane of Quadruples of Single Precision Floating-Point Values</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>VPERMILPS
— Permute In-Lane of Quadruples of Single Precision Floating-Point Values</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op / En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>VEX.128.66.0F38.W0 0C /r VPERMILPS xmm1, xmm2, xmm3/m128</td>
<td>A</td>
<td>V/V</td>
<td>AVX</td>
<td>Permute single-precision floating-point values in xmm2 using controls from xmm3/m128 and store result in xmm1.</td></tr>
<tr>
<td>VEX.128.66.0F3A.W0 04 /r ib VPERMILPS xmm1, xmm2/m128, imm8</td>
<td>B</td>
<td>V/V</td>
<td>AVX</td>
<td>Permute single-precision floating-point values in xmm2/m128 using controls from imm8 and store result in xmm1.</td></tr>
<tr>
<td>VEX.256.66.0F38.W0 0C /r VPERMILPS ymm1, ymm2, ymm3/m256</td>
<td>A</td>
<td>V/V</td>
<td>AVX</td>
<td>Permute single-precision floating-point values in ymm2 using controls from ymm3/m256 and store result in ymm1.</td></tr>
<tr>
<td>VEX.256.66.0F3A.W0 04 /r ib VPERMILPS ymm1, ymm2/m256, imm8</td>
<td>B</td>
<td>V/V</td>
<td>AVX</td>
<td>Permute single-precision floating-point values in ymm2/m256 using controls from imm8 and store result in ymm1.</td></tr>
<tr>
<td>EVEX.128.66.0F38.W0 0C /r VPERMILPS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst</td>
<td>C</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Permute single-precision floating-point values xmm2 using control from xmm3/m128/m32bcst and store the result in xmm1 using writemask k1.</td></tr>
<tr>
<td>EVEX.256.66.0F38.W0 0C /r VPERMILPS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst</td>
<td>C</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Permute single-precision floating-point values ymm2 using control from ymm3/m256/m32bcst and store the result in ymm1 using writemask k1.</td></tr>
<tr>
<td>EVEX.512.66.0F38.W0 0C /r VPERMILPS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst</td>
<td>C</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Permute single-precision floating-point values zmm2 using control from zmm3/m512/m32bcst and store the result in zmm1 using writemask k1.</td></tr>
<tr>
<td>EVEX.128.66.0F3A.W0 04 /r ib VPERMILPS xmm1 {k1}{z}, xmm2/m128/m32bcst, imm8</td>
<td>D</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Permute single-precision floating-point values xmm2/m128/m32bcst using controls from imm8 and store the result in xmm1 using writemask k1.</td></tr>
<tr>
<td>EVEX.256.66.0F3A.W0 04 /r ib VPERMILPS ymm1 {k1}{z}, ymm2/m256/m32bcst, imm8</td>
<td>D</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Permute single-precision floating-point values ymm2/m256/m32bcst using controls from imm8 and store the result in ymm1 using writemask k1.</td></tr>
<tr>
<td>EVEX.512.66.0F3A.W0 04 /r ibVPERMILPS zmm1 {k1}{z}, zmm2/m512/m32bcst, imm8</td>
<td>D</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Permute single-precision floating-point values zmm2/m512/m32bcst using controls from imm8 and store the result in zmm1 using writemask k1.</td></tr></table>
<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
</a></h2>
<table>
<tr>
<th>Op/En</th>
<th>Tuple Type</th>
<th>Operand 1</th>
<th>Operand 2</th>
<th>Operand 3</th>
<th>Operand 4</th></tr>
<tr>
<td>A</td>
<td>N/A</td>
<td>ModRM:reg (w)</td>
<td>VEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>N/A</td></tr>
<tr>
<td>B</td>
<td>N/A</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>N/A</td>
<td>N/A</td></tr>
<tr>
<td>C</td>
<td>Full</td>
<td>ModRM:reg (w)</td>
<td>EVEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>N/A</td></tr>
<tr>
<td>D</td>
<td>Full</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>N/A</td>
<td>N/A</td></tr></table>
<h3 id="description">Description<a class="anchor" href="#description">
</a></h3>
<p>Variable control version:</p>
<p>Permute quadruples of single-precision floating-point values in the first source operand (second operand), each quadruplet using a 2-bit control field in the corresponding dword element of the second source operand. Permuted results are stored in the destination operand (first operand).</p>
<p>The 2-bit control fields are located at the low two bits of each dword element (see <a href='vpermilps.html#fig-5-26'>Figure 5-26</a>). Each control determines which of the source element in an input quadruple is selected for the destination element. Each quadruple of source elements must lie in the same 128-bit region as the destination.</p>
<p>EVEX version: The second source operand (third operand) is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 32-bit memory location. Permuted results are written to the destination under the writemask.</p>
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<figcaption><a href='vpermilps.html#fig-5-25'>Figure 5-25</a>. VPERMILPS Operation</figcaption></figure>
<figure id="fig-5-26">
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<figcaption><a href='vpermilps.html#fig-5-26'>Figure 5-26</a>. VPERMILPS Shuffle Control</figcaption></figure>
<p>(immediate control version)</p>
<p>Permute quadruples of single-precision floating-point values in the first source operand (second operand), each quadruplet using a 2-bit control field in the imm8 byte. Each 128-bit lane in the destination operand (first operand) use the four control fields of the same imm8 byte.</p>
<p>VEX version: The source operand is a YMM/XMM register or a 256/128-bit memory location and the destination operand is a YMM/XMM register.</p>
<p>EVEX version: The source operand (second operand) is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 32-bit memory location. Permuted results are written to the destination under the writemask.</p>
<p>Note: For the imm8 version, VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instruction will #UD.</p>
<h3 id="operation">Operation<a class="anchor" href="#operation">
</a></h3>
<pre>Select4(SRC, control) {
CASE (control[1:0]) OF
0: TMP := SRC[31:0];
1: TMP := SRC[63:32];
2: TMP := SRC[95:64];
3: TMP := SRC[127:96];
ESAC;
RETURN TMP
}
</pre>
<h4 id="vpermilps--evex-immediate-versions-">VPERMILPS (EVEX immediate versions)<a class="anchor" href="#vpermilps--evex-immediate-versions-">
</a></h4>
<pre>(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF (EVEX.b = 1) AND (SRC1 *is memory*)
THEN TMP_SRC1[i+31:i] := SRC1[31:0];
ELSE TMP_SRC1[i+31:i] := SRC1[i+31:i];
FI;
ENDFOR;
TMP_DEST[31:0] := Select4(TMP_SRC1[127:0], imm8[1:0]);
TMP_DEST[63:32] := Select4(TMP_SRC1[127:0], imm8[3:2]);
TMP_DEST[95:64] := Select4(TMP_SRC1[127:0], imm8[5:4]);
TMP_DEST[127:96] := Select4(TMP_SRC1[127:0], imm8[7:6]); FI;
IF VL &gt;= 256
TMP_DEST[159:128] := Select4(TMP_SRC1[255:128], imm8[1:0]); FI;
TMP_DEST[191:160] := Select4(TMP_SRC1[255:128], imm8[3:2]); FI;
TMP_DEST[223:192] := Select4(TMP_SRC1[255:128], imm8[5:4]); FI;
TMP_DEST[255:224] := Select4(TMP_SRC1[255:128], imm8[7:6]); FI;
FI;
IF VL &gt;= 512
TMP_DEST[287:256] := Select4(TMP_SRC1[383:256], imm8[1:0]); FI;
TMP_DEST[319:288] := Select4(TMP_SRC1[383:256], imm8[3:2]); FI;
TMP_DEST[351:320] := Select4(TMP_SRC1[383:256], imm8[5:4]); FI;
TMP_DEST[383:352] := Select4(TMP_SRC1[383:256], imm8[7:6]); FI;
TMP_DEST[415:384] := Select4(TMP_SRC1[511:384], imm8[1:0]); FI;
TMP_DEST[447:416] := Select4(TMP_SRC1[511:384], imm8[3:2]); FI;
TMP_DEST[479:448] := Select4(TMP_SRC1[511:384], imm8[5:4]); FI;
TMP_DEST[511:480] := Select4(TMP_SRC1[511:384], imm8[7:6]); FI;
FI;
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] := TMP_DEST[i+31:i]
ELSE
IF *merging-masking*
THEN *DEST[i+31:i] remains unchanged*
ELSE DEST[i+31:i] := 0 ;zeroing-masking
FI;
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
</pre>
<h4 id="vpermilps--256-bit-immediate-version-">VPERMILPS (256-bit immediate version)<a class="anchor" href="#vpermilps--256-bit-immediate-version-">
</a></h4>
<pre>DEST[31:0] := Select4(SRC1[127:0], imm8[1:0]);
DEST[63:32] := Select4(SRC1[127:0], imm8[3:2]);
DEST[95:64] := Select4(SRC1[127:0], imm8[5:4]);
DEST[127:96] := Select4(SRC1[127:0], imm8[7:6]);
DEST[159:128] := Select4(SRC1[255:128], imm8[1:0]);
DEST[191:160] := Select4(SRC1[255:128], imm8[3:2]);
DEST[223:192] := Select4(SRC1[255:128], imm8[5:4]);
DEST[255:224] := Select4(SRC1[255:128], imm8[7:6]);
</pre>
<h4 id="vpermilps--128-bit-immediate-version-">VPERMILPS (128-bit immediate version)<a class="anchor" href="#vpermilps--128-bit-immediate-version-">
</a></h4>
<pre>DEST[31:0] := Select4(SRC1[127:0], imm8[1:0]);
DEST[63:32] := Select4(SRC1[127:0], imm8[3:2]);
DEST[95:64] := Select4(SRC1[127:0], imm8[5:4]);
DEST[127:96] := Select4(SRC1[127:0], imm8[7:6]);
DEST[MAXVL-1:128] := 0
</pre>
<h4 id="vpermilps--evex-variable-versions-">VPERMILPS (EVEX variable versions)<a class="anchor" href="#vpermilps--evex-variable-versions-">
</a></h4>
<pre>(KL, VL) = (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN TMP_SRC2[i+31:i] := SRC2[31:0];
ELSE TMP_SRC2[i+31:i] := SRC2[i+31:i];
FI;
ENDFOR;
TMP_DEST[31:0] := Select4(SRC1[127:0], TMP_SRC2[1:0]);
TMP_DEST[63:32] := Select4(SRC1[127:0], TMP_SRC2[33:32]);
TMP_DEST[95:64] := Select4(SRC1[127:0], TMP_SRC2[65:64]);
TMP_DEST[127:96] := Select4(SRC1[127:0], TMP_SRC2[97:96]);
IF VL &gt;= 256
TMP_DEST[159:128] := Select4(SRC1[255:128], TMP_SRC2[129:128]);
TMP_DEST[191:160] := Select4(SRC1[255:128], TMP_SRC2[161:160]);
TMP_DEST[223:192] := Select4(SRC1[255:128], TMP_SRC2[193:192]);
TMP_DEST[255:224] := Select4(SRC1[255:128], TMP_SRC2[225:224]);
FI;
IF VL &gt;= 512
TMP_DEST[287:256] := Select4(SRC1[383:256], TMP_SRC2[257:256]);
TMP_DEST[319:288] := Select4(SRC1[383:256], TMP_SRC2[289:288]);
TMP_DEST[351:320] := Select4(SRC1[383:256], TMP_SRC2[321:320]);
TMP_DEST[383:352] := Select4(SRC1[383:256], TMP_SRC2[353:352]);
TMP_DEST[415:384] := Select4(SRC1[511:384], TMP_SRC2[385:384]);
TMP_DEST[447:416] := Select4(SRC1[511:384], TMP_SRC2[417:416]);
TMP_DEST[479:448] := Select4(SRC1[511:384], TMP_SRC2[449:448]);
TMP_DEST[511:480] := Select4(SRC1[511:384], TMP_SRC2[481:480]);
FI;
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] := TMP_DEST[i+31:i]
ELSE
IF *merging-masking*
THEN *DEST[i+31:i] remains unchanged*
ELSE DEST[i+31:i] := 0 ;zeroing-masking
FI;
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
</pre>
<h4 id="vpermilps--256-bit-variable-version-">VPERMILPS (256-bit variable version)<a class="anchor" href="#vpermilps--256-bit-variable-version-">
</a></h4>
<pre>DEST[31:0] := Select4(SRC1[127:0], SRC2[1:0]);
DEST[63:32] := Select4(SRC1[127:0], SRC2[33:32]);
DEST[95:64] := Select4(SRC1[127:0], SRC2[65:64]);
DEST[127:96] := Select4(SRC1[127:0], SRC2[97:96]);
DEST[159:128] := Select4(SRC1[255:128], SRC2[129:128]);
DEST[191:160] := Select4(SRC1[255:128], SRC2[161:160]);
DEST[223:192] := Select4(SRC1[255:128], SRC2[193:192]);
DEST[255:224] := Select4(SRC1[255:128], SRC2[225:224]);
DEST[MAXVL-1:256] := 0
</pre>
<h4 id="vpermilps--128-bit-variable-version-">VPERMILPS (128-bit variable version)<a class="anchor" href="#vpermilps--128-bit-variable-version-">
</a></h4>
<pre>DEST[31:0] := Select4(SRC1[127:0], SRC2[1:0]);
DEST[63:32] := Select4(SRC1[127:0], SRC2[33:32]);
DEST[95:64] :=Select4(SRC1[127:0], SRC2[65:64]);
DEST[127:96] := Select4(SRC1[127:0], SRC2[97:96]);
DEST[MAXVL-1:128] := 0
</pre>
<h3 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
</a></h3>
<pre>VPERMILPS __m512 _mm512_permute_ps( __m512 a, int imm);
</pre>
<pre>VPERMILPS __m512 _mm512_mask_permute_ps(__m512 s, __mmask16 k, __m512 a, int imm);
</pre>
<pre>VPERMILPS __m512 _mm512_maskz_permute_ps( __mmask16 k, __m512 a, int imm);
</pre>
<pre>VPERMILPS __m256 _mm256_mask_permute_ps(__m256 s, __mmask8 k, __m256 a, int imm);
</pre>
<pre>VPERMILPS __m256 _mm256_maskz_permute_ps( __mmask8 k, __m256 a, int imm);
</pre>
<pre>VPERMILPS __m128 _mm_mask_permute_ps(__m128 s, __mmask8 k, __m128 a, int imm);
</pre>
<pre>VPERMILPS __m128 _mm_maskz_permute_ps( __mmask8 k, __m128 a, int imm);
</pre>
<pre>VPERMILPS __m512 _mm512_permutevar_ps( __m512i i, __m512 a);
</pre>
<pre>VPERMILPS __m512 _mm512_mask_permutevar_ps(__m512 s, __mmask16 k, __m512i i, __m512 a);
</pre>
<pre>VPERMILPS __m512 _mm512_maskz_permutevar_ps( __mmask16 k, __m512i i, __m512 a);
</pre>
<pre>VPERMILPS __m256 _mm256_mask_permutevar_ps(__m256 s, __mmask8 k, __m256 i, __m256 a);
</pre>
<pre>VPERMILPS __m256 _mm256_maskz_permutevar_ps( __mmask8 k, __m256 i, __m256 a);
</pre>
<pre>VPERMILPS __m128 _mm_mask_permutevar_ps(__m128 s, __mmask8 k, __m128 i, __m128 a);
</pre>
<pre>VPERMILPS __m128 _mm_maskz_permutevar_ps( __mmask8 k, __m128 i, __m128 a);
</pre>
<pre>VPERMILPS __m128 _mm_permute_ps (__m128 a, int control);
</pre>
<pre>VPERMILPS __m256 _mm256_permute_ps (__m256 a, int control);
</pre>
<pre>VPERMILPS __m128 _mm_permutevar_ps (__m128 a, __m128i control);
</pre>
<pre>VPERMILPS __m256 _mm256_permutevar_ps (__m256 a, __m256i control);
</pre>
<h3 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
</a></h3>
<p>None.</p>
<h3 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
</a></h3>
<p>Non-EVEX-encoded instruction, see <span class="not-imported">Table 2-21</span>, “Type 4 Class Exception Conditions.”</p>
<p>Additionally:</p>
<table>
<tr>
<td>#UD</td>
<td>If VEX.W = 1.</td></tr></table>
<p>EVEX-encoded instruction, see <span class="not-imported">Table 2-50</span>, “Type E4NF Class Exception Conditions.”</p>
<p>Additionally:</p>
<table>
<tr>
<td>#UD</td>
<td>If either (E)VEX.vvvv != 1111B and with imm8.</td></tr></table><footer><p>
This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
</p></footer></body></html>
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