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119 lines
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119 lines
4.7 KiB
HTML
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>VPBROADCASTM
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— Broadcast Mask to Vector Register</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>VPBROADCASTM
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— Broadcast Mask to Vector Register</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>EVEX.128.F3.0F38.W1 2A /r VPBROADCASTMB2Q xmm1, k1</td>
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<td>RM</td>
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<td>V/V</td>
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<td>AVX512VL AVX512CD</td>
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<td>Broadcast low byte value in k1 to two locations in xmm1.</td></tr>
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<tr>
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<td>EVEX.256.F3.0F38.W1 2A /r VPBROADCASTMB2Q ymm1, k1</td>
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<td>RM</td>
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<td>V/V</td>
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<td>AVX512VL AVX512CD</td>
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<td>Broadcast low byte value in k1 to four locations in ymm1.</td></tr>
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<tr>
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<td>EVEX.512.F3.0F38.W1 2A /r VPBROADCASTMB2Q zmm1, k1</td>
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<td>RM</td>
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<td>V/V</td>
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<td>AVX512CD</td>
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<td>Broadcast low byte value in k1 to eight locations in zmm1.</td></tr>
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<tr>
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<td>EVEX.128.F3.0F38.W0 3A /r VPBROADCASTMW2D xmm1, k1</td>
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<td>RM</td>
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<td>V/V</td>
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<td>AVX512VL AVX512CD</td>
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<td>Broadcast low word value in k1 to four locations in xmm1.</td></tr>
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<tr>
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<td>EVEX.256.F3.0F38.W0 3A /r VPBROADCASTMW2D ymm1, k1</td>
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<td>RM</td>
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<td>V/V</td>
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<td>AVX512VL AVX512CD</td>
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<td>Broadcast low word value in k1 to eight locations in ymm1.</td></tr>
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<tr>
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<td>EVEX.512.F3.0F38.W0 3A /r VPBROADCASTMW2D zmm1, k1</td>
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<td>RM</td>
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<td>V/V</td>
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<td>AVX512CD</td>
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<td>Broadcast low word value in k1 to sixteen locations in zmm1.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>RM</td>
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<td>ModRM:reg (w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h3 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h3>
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<p>Broadcasts the zero-extended 64/32 bit value of the low byte/word of the source operand (the second operand) to each 64/32 bit element of the destination operand (the first operand). The source operand is an opmask register. The destination operand is a ZMM register (EVEX.512), YMM register (EVEX.256), or XMM register (EVEX.128).</p>
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<p>EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.</p>
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<h3 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h3>
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<h4 id="vpbroadcastmb2q">VPBROADCASTMB2Q<a class="anchor" href="#vpbroadcastmb2q">
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¶
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</a></h4>
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<pre>(KL, VL) = (2, 128), (4, 256), (8, 512)
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FOR j := 0 TO KL-1
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i := j*64
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DEST[i+63:i] := ZeroExtend(SRC[7:0])
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ENDFOR
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DEST[MAXVL-1:VL] := 0
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</pre>
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<h4 id="vpbroadcastmw2d">VPBROADCASTMW2D<a class="anchor" href="#vpbroadcastmw2d">
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¶
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</a></h4>
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<pre>(KL, VL) = (4, 128), (8, 256),(16, 512)
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FOR j := 0 TO KL-1
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i := j*32
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DEST[i+31:i] := ZeroExtend(SRC[15:0])
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ENDFOR
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DEST[MAXVL-1:VL] := 0
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</pre>
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<h3 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h3>
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<pre>VPBROADCASTMB2Q __m512i _mm512_broadcastmb_epi64( __mmask8);
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</pre>
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<pre>VPBROADCASTMW2D __m512i _mm512_broadcastmw_epi32( __mmask16);
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</pre>
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<pre>VPBROADCASTMB2Q __m256i _mm256_broadcastmb_epi64( __mmask8);
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</pre>
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<pre>VPBROADCASTMW2D __m256i _mm256_broadcastmw_epi32( __mmask8);
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</pre>
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<pre>VPBROADCASTMB2Q __m128i _mm_broadcastmb_epi64( __mmask8);
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</pre>
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<pre>VPBROADCASTMW2D __m128i _mm_broadcastmw_epi32( __mmask8);
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</pre>
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<h3 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h3>
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<p>None</p>
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<h3 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h3>
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<p>EVEX-encoded instruction, see <span class="not-imported">Table 2-54</span>, “Type E6NF Class Exception Conditions.”</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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