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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS
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— Fused Negative Multiply-Subtract ofScalar Single Precision Floating-Point Values</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS
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— Fused Negative Multiply-Subtract ofScalar Single Precision Floating-Point Values</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op / En</th>
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<th>64/32 Bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>VEX.LIG.66.0F38.W0 9F /r VFNMSUB132SS xmm1, xmm2, xmm3/m32</td>
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<td>A</td>
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<td>V/V</td>
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<td>FMA</td>
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<td>Multiply scalar single-precision floating-point value from xmm1 and xmm3/m32, negate the multiplication result and subtract xmm2 and put result in xmm1.</td></tr>
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<tr>
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<td>VEX.LIG.66.0F38.W0 AF /r VFNMSUB213SS xmm1, xmm2, xmm3/m32</td>
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<td>A</td>
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<td>V/V</td>
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<td>FMA</td>
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<td>Multiply scalar single-precision floating-point value from xmm1 and xmm2, negate the multiplication result and subtract xmm3/m32 and put result in xmm1.</td></tr>
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<tr>
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<td>VEX.LIG.66.0F38.W0 BF /r VFNMSUB231SS xmm1, xmm2, xmm3/m32</td>
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<td>A</td>
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<td>V/V</td>
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<td>FMA</td>
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<td>Multiply scalar single-precision floating-point value from xmm2 and xmm3/m32, negate the multiplication result and subtract xmm1 and put result in xmm1.</td></tr>
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<tr>
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<td>EVEX.LLIG.66.0F38.W0 9F /r VFNMSUB132SS xmm1 {k1}{z}, xmm2, xmm3/m32{er}</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX512F</td>
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<td>Multiply scalar single-precision floating-point value from xmm1 and xmm3/m32, negate the multiplication result and subtract xmm2 and put result in xmm1.</td></tr>
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<tr>
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<td>EVEX.LLIG.66.0F38.W0 AF /r VFNMSUB213SS xmm1 {k1}{z}, xmm2, xmm3/m32{er}</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX512F</td>
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<td>Multiply scalar single-precision floating-point value from xmm1 and xmm2, negate the multiplication result and subtract xmm3/m32 and put result in xmm1.</td></tr>
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<tr>
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<td>EVEX.LLIG.66.0F38.W0 BF /r VFNMSUB231SS xmm1 {k1}{z}, xmm2, xmm3/m32{er}</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX512F</td>
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<td>Multiply scalar single-precision floating-point value from xmm2 and xmm3/m32, negate the multiplication result and subtract xmm1 and put result in xmm1.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple Type</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>N/A</td>
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<td>ModRM:reg (r, w)</td>
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<td>VEX.vvvv (r)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td></tr>
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<tr>
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<td>B</td>
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<td>Tuple1 Scalar</td>
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<td>ModRM:reg (r, w)</td>
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<td>EVEX.vvvv (r)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td></tr></table>
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<h3 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h3>
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<p>VFNMSUB132SS: Multiplies the low packed single-precision floating-point value from the first source operand to the low packed single-precision floating-point value in the third source operand. From negated infinite precision intermediate result, the low single-precision floating-point value in the second source operand, performs rounding and stores the resulting packed single-precision floating-point value to the destination operand (first source operand).</p>
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<p>VFNMSUB213SS: Multiplies the low packed single-precision floating-point value from the second source operand to the low packed single-precision floating-point value in the first source operand. From negated infinite precision intermediate result, the low single-precision floating-point value in the third source operand, performs rounding and stores the resulting packed single-precision floating-point value to the destination operand (first source operand).</p>
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<p>VFNMSUB231SS: Multiplies the low packed single-precision floating-point value from the second source to the low packed single-precision floating-point value in the third source operand. From negated infinite precision intermediate result, the low single-precision floating-point value in the first source operand, performs rounding and stores the resulting packed single-precision floating-point value to the destination operand (first source operand).</p>
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<p>VEX.128 and EVEX encoded version: The destination operand (also first source operand) is encoded in reg_field. The second source operand is encoded in VEX.vvvv/EVEX.vvvv. The third source operand is encoded in rm_field. Bits 127:32 of the destination are unchanged. Bits MAXVL-1:128 of the destination register are zeroed.</p>
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<p>EVEX encoded version: The low doubleword element of the destination is updated according to the writemask.</p>
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<p>Compiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the opcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations</p>
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<p>involving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction column.</p>
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<h3 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h3>
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<pre>In the operations below, “*” and “-” symbols represent multiplication and subtraction with infinite precision inputs and outputs (no
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rounding).
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</pre>
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<h4 id="vfnmsub132ss-dest--src2--src3--evex-encoded-version-">VFNMSUB132SS DEST, SRC2, SRC3 (EVEX encoded version)<a class="anchor" href="#vfnmsub132ss-dest--src2--src3--evex-encoded-version-">
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¶
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</a></h4>
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<pre>IF (EVEX.b = 1) and SRC3 *is a register*
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THEN
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SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);
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ELSE
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SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);
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FI;
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IF k1[0] or *no writemask*
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THEN DEST[31:0] := RoundFPControl(-(DEST[31:0]*SRC3[31:0]) - SRC2[31:0])
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ELSE
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IF *merging-masking* ; merging-masking
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THEN *DEST[31:0] remains unchanged*
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ELSE ; zeroing-masking
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THEN DEST[31:0] := 0
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FI;
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FI;
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DEST[127:32] := DEST[127:32]
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DEST[MAXVL-1:128] := 0
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</pre>
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<h4 id="vfnmsub213ss-dest--src2--src3--evex-encoded-version-">VFNMSUB213SS DEST, SRC2, SRC3 (EVEX encoded version)<a class="anchor" href="#vfnmsub213ss-dest--src2--src3--evex-encoded-version-">
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¶
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</a></h4>
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<pre>IF (EVEX.b = 1) and SRC3 *is a register*
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THEN
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SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);
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ELSE
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SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);
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FI;
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IF k1[0] or *no writemask*
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THEN DEST[31:0] := RoundFPControl(-(SRC2[31:0]*DEST[31:0]) - SRC3[31:0])
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ELSE
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IF *merging-masking* ; merging-masking
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THEN *DEST[31:0] remains unchanged*
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ELSE ; zeroing-masking
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THEN DEST[31:0] := 0
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FI;
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FI;
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DEST[127:32] := DEST[127:32]
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DEST[MAXVL-1:128] := 0
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</pre>
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<h4 id="vfnmsub231ss-dest--src2--src3--evex-encoded-version-">VFNMSUB231SS DEST, SRC2, SRC3 (EVEX encoded version)<a class="anchor" href="#vfnmsub231ss-dest--src2--src3--evex-encoded-version-">
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¶
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</a></h4>
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<pre>IF (EVEX.b = 1) and SRC3 *is a register*
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THEN
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SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);
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ELSE
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SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);
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FI;
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IF k1[0] or *no writemask*
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THEN DEST[31:0] := RoundFPControl(-(SRC2[31:0]*SRC3[63:0]) - DEST[31:0])
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ELSE
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IF *merging-masking* ; merging-masking
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THEN *DEST[31:0] remains unchanged*
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ELSE ; zeroing-masking
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THEN DEST[31:0] := 0
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FI;
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FI;
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DEST[127:32] := DEST[127:32]
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DEST[MAXVL-1:128] := 0
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</pre>
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<h4 id="vfnmsub132ss-dest--src2--src3--vex-encoded-version-">VFNMSUB132SS DEST, SRC2, SRC3 (VEX encoded version)<a class="anchor" href="#vfnmsub132ss-dest--src2--src3--vex-encoded-version-">
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¶
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</a></h4>
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<pre>DEST[31:0] := RoundFPControl_MXCSR(- (DEST[31:0]*SRC3[31:0]) - SRC2[31:0])
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DEST[127:32] := DEST[127:32]
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DEST[MAXVL-1:128] := 0
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</pre>
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<h4 id="vfnmsub213ss-dest--src2--src3--vex-encoded-version-">VFNMSUB213SS DEST, SRC2, SRC3 (VEX encoded version)<a class="anchor" href="#vfnmsub213ss-dest--src2--src3--vex-encoded-version-">
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¶
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</a></h4>
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<pre>DEST[31:0] := RoundFPControl_MXCSR(- (SRC2[31:0]*DEST[31:0]) - SRC3[31:0])
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DEST[127:32] := DEST[127:32]
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DEST[MAXVL-1:128] := 0
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</pre>
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<h4 id="vfnmsub231ss-dest--src2--src3--vex-encoded-version-">VFNMSUB231SS DEST, SRC2, SRC3 (VEX encoded version)<a class="anchor" href="#vfnmsub231ss-dest--src2--src3--vex-encoded-version-">
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¶
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</a></h4>
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<pre>DEST[31:0] := RoundFPControl_MXCSR(- (SRC2[31:0]*SRC3[31:0]) - DEST[31:0])
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DEST[127:32] := DEST[127:32]
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DEST[MAXVL-1:128] := 0
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</pre>
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<h3 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h3>
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<pre>VFNMSUBxxxSS __m128 _mm_fnmsub_round_ss(__m128 a, __m128 b, __m128 c, int r);
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</pre>
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<pre>VFNMSUBxxxSS __m128 _mm_mask_fnmsub_ss(__m128 a, __mmask8 k, __m128 b, __m128 c);
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</pre>
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<pre>VFNMSUBxxxSS __m128 _mm_maskz_fnmsub_ss(__mmask8 k, __m128 a, __m128 b, __m128 c);
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</pre>
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<pre>VFNMSUBxxxSS __m128 _mm_mask3_fnmsub_ss(__m128 a, __m128 b, __m128 c, __mmask8 k);
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</pre>
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<pre>VFNMSUBxxxSS __m128 _mm_mask_fnmsub_round_ss(__m128 a, __mmask8 k, __m128 b, __m128 c, int r);
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</pre>
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<pre>VFNMSUBxxxSS __m128 _mm_maskz_fnmsub_round_ss(__mmask8 k, __m128 a, __m128 b, __m128 c, int r);
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</pre>
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<pre>VFNMSUBxxxSS __m128 _mm_mask3_fnmsub_round_ss(__m128 a, __m128 b, __m128 c, __mmask8 k, int r);
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</pre>
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<pre>VFNMSUBxxxSS __m128 _mm_fnmsub_ss (__m128 a, __m128 b, __m128 c);
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</pre>
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<h3 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h3>
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<p>Overflow, Underflow, Invalid, Precision, Denormal.</p>
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<h3 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h3>
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<p>VEX-encoded instructions, see <span class="not-imported">Table 2-20</span>, “Type 3 Class Exception Conditions.”</p>
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<p>EVEX-encoded instructions, see <span class="not-imported">Table 2-47</span>, “Type E3 Class Exception Conditions.”</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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