forked from NRZCode/ia32-64
120 lines
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120 lines
5.7 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>VEXP2PS
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— Approximation to the Exponential 2^x of Packed Single Precision Floating-PointValues With Less Than 2^-23 Relative Error</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>VEXP2PS
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— Approximation to the Exponential 2^x of Packed Single Precision Floating-PointValues With Less Than 2^-23 Relative Error</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>EVEX.512.66.0F38.W0 C8 /r VEXP2PS zmm1 {k1}{z}, zmm2/m512/m32bcst {sae}</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512ER</td>
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<td>Computes approximations to the exponential 2^x (with less than 2^-23 of maximum relative error) of the packed single-precision floating-point values from zmm2/m512/m32bcst and stores the floating-point result in zmm1with writemask k1.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En Tuple Type Operand 1 Operand 2 Operand 3 Operand 4</th>
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<th></th>
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<th></th>
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<th></th>
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<th></th>
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<th></th></tr>
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<tr>
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<td>A Full ModRM:reg (r, w) ModRM:r/m (r) N/A N/A</td>
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<td></td>
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<td></td>
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<td></td>
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<td></td>
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<td></td></tr></table>
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<h3 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h3>
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<p>Computes the approximate base-2 exponential evaluation of the single-precision floating-point values in the source operand (the second operand) and store the results in the destination operand (the first operand) using the write-mask k1. The approximate base-2 exponential is evaluated with less than 2^-23 of relative error.</p>
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<p>Denormal input values are treated as zeros and do not signal #DE, irrespective of MXCSR.DAZ. Denormal results are flushed to zeros and do not signal #UE, irrespective of MXCSR.FTZ.</p>
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<p>The source operand is a ZMM register, a 512-bit memory location, or a 512-bit vector broadcasted from a 32-bit memory location. The destination operand is a ZMM register, conditionally updated using writemask k1.</p>
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<p>EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.</p>
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<h3 id="a-numerically-exact-implementation-of-vexp2xx-can-be-found-at-https---software-intel-com-en-us-articles-refer-">A numerically exact implementation of VEXP2xx can be found at https://software.intel.com/en-us/articles/refer-<a class="anchor" href="#a-numerically-exact-implementation-of-vexp2xx-can-be-found-at-https---software-intel-com-en-us-articles-refer-">
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¶
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</a></h3>
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<h3 id="ence-implementations-for-ia-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2-">ence-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.<a class="anchor" href="#ence-implementations-for-ia-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2-">
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¶
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</a></h3>
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<h3 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h3>
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<h4 id="vexp2ps">VEXP2PS<a class="anchor" href="#vexp2ps">
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¶
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</a></h4>
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<pre>(KL, VL) = (16, 512)
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FOR j := 0 TO KL-1
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i := j * 32
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IF k1[j] OR *no writemask* THEN
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IF (EVEX.b = 1) AND (SRC *is memory*)
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THEN DEST[i+31:i] := EXP2_23_SP(SRC[31:0])
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ELSE DEST[i+31:i] := EXP2_23_SP(SRC[i+31:i])
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FI;
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ELSE
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IF *merging-masking* ; merging-masking
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THEN *DEST[i+31:i] remains unchanged*
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ELSE ; zeroing-masking
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DEST[i+31:i] := 0
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FI;
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FI;
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ENDFOR;
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</pre>
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<figure id="tbl-6-45">
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<table>
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<tr>
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<th>Source Input</th>
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<th>Result</th>
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<th>Comments</th></tr>
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<tr>
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<td>NaN</td>
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<td>QNaN(src)</td>
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<td>If (SRC = SNaN) then #I</td></tr>
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<tr>
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<td>+∞</td>
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<td>+∞</td>
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<td></td></tr>
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<tr>
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<td>+/-0</td>
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<td>1.0f</td>
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<td>Exact result</td></tr>
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<tr>
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<td>-∞</td>
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<td>+0.0f</td>
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<td></td></tr>
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<tr>
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<td>Integral value N</td>
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<td>2^ (N)</td>
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<td>Exact result</td></tr></table>
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<figcaption><a href='vexp2ps.html#tbl-6-45'>Table 6-45</a>. Special Values Behavior</figcaption></figure>
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<h3 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h3>
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<pre>VEXP2PS __m512 _mm512_exp2a23_round_ps (__m512 a, int sae);
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</pre>
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<pre>VEXP2PS __m512 _mm512_mask_exp2a23_round_ps (__m512 a, __mmask16 m, __m512 b, int sae);
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</pre>
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<pre>VEXP2PS __m512 _mm512_maskz_exp2a23_round_ps (__mmask16 m, __m512 b, int sae);
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</pre>
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<h3 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h3>
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<p>Invalid (if SNaN input), Overflow.</p>
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<h3 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h3>
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<p>See <span class="not-imported">Table 2-46</span>, “Type E2 Class Exception Conditions.”</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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