forked from NRZCode/ia32-64
143 lines
6.3 KiB
HTML
143 lines
6.3 KiB
HTML
<!DOCTYPE html>
|
||
<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>VCVTUDQ2PD
|
||
— Convert Packed Unsigned Doubleword Integers to Packed Double PrecisionFloating-Point Values</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>VCVTUDQ2PD
|
||
— Convert Packed Unsigned Doubleword Integers to Packed Double PrecisionFloating-Point Values</h1>
|
||
|
||
<table>
|
||
<tr>
|
||
<th>Opcode/Instruction</th>
|
||
<th>Op/En</th>
|
||
<th>64/32 Bit Mode Support</th>
|
||
<th>CPUID Feature Flag</th>
|
||
<th>Description</th></tr>
|
||
<tr>
|
||
<td>EVEX.128.F3.0F.W0 7A /r VCVTUDQ2PD xmm1 {k1}{z}, xmm2/m64/m32bcst</td>
|
||
<td>A</td>
|
||
<td>V/V</td>
|
||
<td>AVX512VL AVX512F</td>
|
||
<td>Convert two packed unsigned doubleword integers from ymm2/m64/m32bcst to packed double precision floating-point values in zmm1 with writemask k1.</td></tr>
|
||
<tr>
|
||
<td>EVEX.256.F3.0F.W0 7A /r VCVTUDQ2PD ymm1 {k1}{z}, xmm2/m128/m32bcst</td>
|
||
<td>A</td>
|
||
<td>V/V</td>
|
||
<td>AVX512VL AVX512F</td>
|
||
<td>Convert four packed unsigned doubleword integers from xmm2/m128/m32bcst to packed double precision floating-point values in zmm1 with writemask k1.</td></tr>
|
||
<tr>
|
||
<td>EVEX.512.F3.0F.W0 7A /r VCVTUDQ2PD zmm1 {k1}{z}, ymm2/m256/m32bcst</td>
|
||
<td>A</td>
|
||
<td>V/V</td>
|
||
<td>AVX512F</td>
|
||
<td>Convert eight packed unsigned doubleword integers from ymm2/m256/m32bcst to eight packed double precision floating-point values in zmm1 with writemask k1.</td></tr></table>
|
||
<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
|
||
¶
|
||
</a></h2>
|
||
<table>
|
||
<tr>
|
||
<th>Op/En</th>
|
||
<th>Tuple Type</th>
|
||
<th>Operand 1</th>
|
||
<th>Operand 2</th>
|
||
<th>Operand 3</th>
|
||
<th>Operand 4</th></tr>
|
||
<tr>
|
||
<td>A</td>
|
||
<td>Half</td>
|
||
<td>ModRM:reg (w)</td>
|
||
<td>ModRM:r/m (r)</td>
|
||
<td>N/A</td>
|
||
<td>N/A</td></tr></table>
|
||
<h3 id="description">Description<a class="anchor" href="#description">
|
||
¶
|
||
</a></h3>
|
||
<p>Converts packed unsigned doubleword integers in the source operand (second operand) to packed double precision floating-point values in the destination operand (first operand).</p>
|
||
<p>The source operand is a YMM/XMM/XMM (low 64 bits) register, a 256/128/64-bit memory location or a 256/128/64-bit vector broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1.</p>
|
||
<p>Attempt to encode this instruction with EVEX embedded rounding is ignored.</p>
|
||
<p>Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.</p>
|
||
<h3 id="operation">Operation<a class="anchor" href="#operation">
|
||
¶
|
||
</a></h3>
|
||
<h4 id="vcvtudq2pd--evex-encoded-versions--when-src-operand-is-a-register">VCVTUDQ2PD (EVEX Encoded Versions) When SRC Operand is a Register<a class="anchor" href="#vcvtudq2pd--evex-encoded-versions--when-src-operand-is-a-register">
|
||
¶
|
||
</a></h4>
|
||
<pre>(KL, VL) = (2, 128), (4, 256), (8, 512)
|
||
FOR j := 0 TO KL-1
|
||
i := j * 64
|
||
k := j * 32
|
||
IF k1[j] OR *no writemask*
|
||
THEN DEST[i+63:i] :=
|
||
Convert_UInteger_To_Double_Precision_Floating_Point(SRC[k+31:k])
|
||
ELSE
|
||
IF *merging-masking* ; merging-masking
|
||
THEN *DEST[i+63:i] remains unchanged*
|
||
ELSE ; zeroing-masking
|
||
DEST[i+63:i] := 0
|
||
FI
|
||
FI;
|
||
ENDFOR
|
||
DEST[MAXVL-1:VL] := 0
|
||
</pre>
|
||
<h4 id="vcvtudq2pd--evex-encoded-versions--when-src-operand-is-a-memory-source">VCVTUDQ2PD (EVEX Encoded Versions) When SRC Operand is a Memory Source<a class="anchor" href="#vcvtudq2pd--evex-encoded-versions--when-src-operand-is-a-memory-source">
|
||
¶
|
||
</a></h4>
|
||
<pre>(KL, VL) = (2, 128), (4, 256), (8, 512)
|
||
FOR j := 0 TO KL-1
|
||
i := j * 64
|
||
k := j * 32
|
||
IF k1[j] OR *no writemask*
|
||
THEN
|
||
IF (EVEX.b = 1)
|
||
THEN
|
||
DEST[i+63:i] :=
|
||
Convert_UInteger_To_Double_Precision_Floating_Point(SRC[31:0])
|
||
ELSE
|
||
DEST[i+63:i] :=
|
||
Convert_UInteger_To_Double_Precision_Floating_Point(SRC[k+31:k])
|
||
FI;
|
||
ELSE
|
||
IF *merging-masking* ; merging-masking
|
||
THEN *DEST[i+63:i] remains unchanged*
|
||
ELSE ; zeroing-masking
|
||
DEST[i+63:i] := 0
|
||
FI
|
||
FI;
|
||
ENDFOR
|
||
DEST[MAXVL-1:VL] := 0
|
||
</pre>
|
||
<h3 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
|
||
¶
|
||
</a></h3>
|
||
<pre>VCVTUDQ2PD __m512d _mm512_cvtepu32_pd( __m256i a);
|
||
</pre>
|
||
<pre>VCVTUDQ2PD __m512d _mm512_mask_cvtepu32_pd( __m512d s, __mmask8 k, __m256i a);
|
||
</pre>
|
||
<pre>VCVTUDQ2PD __m512d _mm512_maskz_cvtepu32_pd( __mmask8 k, __m256i a);
|
||
</pre>
|
||
<pre>VCVTUDQ2PD __m256d _mm256_cvtepu32_pd( __m128i a);
|
||
</pre>
|
||
<pre>VCVTUDQ2PD __m256d _mm256_mask_cvtepu32_pd( __m256d s, __mmask8 k, __m128i a);
|
||
</pre>
|
||
<pre>VCVTUDQ2PD __m256d _mm256_maskz_cvtepu32_pd( __mmask8 k, __m128i a);
|
||
</pre>
|
||
<pre>VCVTUDQ2PD __m128d _mm_cvtepu32_pd( __m128i a);
|
||
</pre>
|
||
<pre>VCVTUDQ2PD __m128d _mm_mask_cvtepu32_pd( __m128d s, __mmask8 k, __m128i a);
|
||
</pre>
|
||
<pre>VCVTUDQ2PD __m128d _mm_maskz_cvtepu32_pd( __mmask8 k, __m128i a);
|
||
</pre>
|
||
<h3 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
|
||
¶
|
||
</a></h3>
|
||
<p>None.</p>
|
||
<h3 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
|
||
¶
|
||
</a></h3>
|
||
<p>EVEX-encoded instructions, see <span class="not-imported">Table 2-51</span>, “Type E5 Class Exception Conditions.”</p>
|
||
<p>Additionally:</p>
|
||
<table>
|
||
<tr>
|
||
<td>#UD</td>
|
||
<td>If EVEX.vvvv != 1111B.</td></tr></table><footer><p>
|
||
This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
|
||
inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
|
||
ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
|
||
</p></footer></body></html>
|