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89 lines
4.3 KiB
HTML
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>VCVTSH2SI
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— Convert Low FP16 Value to Signed Integer</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>VCVTSH2SI
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— Convert Low FP16 Value to Signed Integer</h1>
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<table>
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<tr>
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<th> Instruction En Bit Mode Flag
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Support Instruction En Bit Mode Flag
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Support 64/32 CPUID Feature Instruction En Bit Mode Flag CPUID Feature Instruction En Bit Mode Flag Op/ 64/32 CPUID Feature Instruction En Bit Mode Flag 64/32 CPUID Feature Instruction En Bit Mode Flag CPUID Feature Instruction En Bit Mode Flag Op/ 64/32 CPUID Feature </th>
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<th></th>
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<th>Support</th>
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<th></th>
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<th>Description</th></tr>
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<tr>
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<td>EVEX.LLIG.F3.MAP5.W0 2D /r VCVTSH2SI r32, xmm1/m16 {er}</td>
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<td>A</td>
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<td>V/V<sup>1</sup></td>
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<td>AVX512-FP16</td>
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<td>Convert the low FP16 element in xmm1/m16 to a signed integer and store the result in r32.</td></tr>
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<tr>
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<td>EVEX.LLIG.F3.MAP5.W1 2D /r VCVTSH2SI r64, xmm1/m16 {er}</td>
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<td>A</td>
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<td>V/N.E.</td>
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<td>AVX512-FP16</td>
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<td>Convert the low FP16 element in xmm1/m16 to a signed integer and store the result in r64.</td></tr></table>
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<blockquote>
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<p>1. Outside of 64b mode, the EVEX.W field is ignored. The instruction behaves as if W=0 was used.</p></blockquote>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>Scalar</td>
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<td>ModRM:reg (w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h3 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h3>
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<p>This instruction converts the low FP16 element in the source operand to a signed integer in the destination general purpose register.</p>
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<p>When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register or the embedded rounding control bits. If a converted result cannot be represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked, the integer indefinite value is returned.</p>
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<h3 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h3>
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<h4 id="vcvtsh2si-dest--src">VCVTSH2SI dest, src<a class="anchor" href="#vcvtsh2si-dest--src">
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¶
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</a></h4>
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<pre>IF *SRC is a register* and (EVEX.b = 1):
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SET_RM(EVEX.RC)
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ELSE:
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SET_RM(MXCSR.RC)
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IF 64-mode and OperandSize == 64:
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DEST.qword := Convert_fp16_to_integer64(SRC.fp16[0])
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ELSE:
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DEST.dword := Convert_fp16_to_integer32(SRC.fp16[0])
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</pre>
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<h3 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h3>
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<pre>VCVTSH2SI int _mm_cvt_roundsh_i32 (__m128h a, int rounding);
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</pre>
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<pre>VCVTSH2SI __int64 _mm_cvt_roundsh_i64 (__m128h a, int rounding);
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</pre>
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<pre>VCVTSH2SI int _mm_cvtsh_i32 (__m128h a);
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</pre>
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<pre>VCVTSH2SI __int64 _mm_cvtsh_i64 (__m128h a);
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</pre>
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<h3 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h3>
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<p>Invalid, Precision.</p>
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<h3 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h3>
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<p>EVEX-encoded instructions, see <span class="not-imported">Table 2-48</span>, “Type E3NF Class Exception Conditions.”</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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