forked from NRZCode/ia32-64
86 lines
3.7 KiB
HTML
86 lines
3.7 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>STTILECFG
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— Store Tile Configuration</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>STTILECFG
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— Store Tile Configuration</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>VEX.128.66.0F38.W0 49 !(11):000:bbb STTILECFG m512</td>
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<td>A</td>
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<td>V/N.E.</td>
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<td>AMX-TILE</td>
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<td>Store tile configuration in m512.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>N/A</td>
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<td>ModRM:r/m (w)</td>
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<td>N/A</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>The STTILECFG instruction takes a pointer to a 64-byte memory location (described in <a href='cpuid.html#tbl-3-10'>Table 3-10</a> in the “LDTILECFG—Load Tile Configuration” entry) that will, after successful execution of this instruction, contain the description of the tiles that were configured. In order to configure tiles, the AMX-TILE bit in CPUID must be set and the operating system has to have enabled the tiles architecture.</p>
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<p>If the tiles are not configured, then STTILECFG stores 64B of zeros to the indicated memory location.</p>
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<p>Any attempt to execute the STTILECFG instruction inside an Intel TSX transaction will result in a transaction abort.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<h3 id="sttilecfg-mem">STTILECFG mem<a class="anchor" href="#sttilecfg-mem">
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¶
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</a></h3>
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<pre>if TILES_CONFIGURED == 0:
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//write 64 bytes of zeros at mem pointer
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buf[0..63] := 0
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write_memory(mem, 64, buf)
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else:
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buf.byte[0] := tilecfg.palette_id
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buf.byte[1] := tilecfg.start_row
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buf.byte[2..15] := 0
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p := 16
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for n in 0 ... palette_table[tilecfg.palette_id].max_names-1:
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buf.word[p/2] := tilecfg.t[n].colsb
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p := p + 2
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if p < 47:
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buf.byte[p..47] := 0
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p := 48
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for n in 0 ... palette_table[tilecfg.palette_id].max_names-1:
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buf.byte[p++] := tilecfg.t[n].rows
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if p < 63:
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buf.byte[p..63] := 0
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write_memory(mem, 64, buf)
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</pre>
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<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h2>
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<pre>STTILECFGvoid _tile_storeconfig(void *);
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</pre>
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<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="exceptions">Exceptions<a class="anchor" href="#exceptions">
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¶
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</a></h2>
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<p>AMX-E2; see Section 2.10, “Intel® AMX Instruction Exception Classes,” for details.</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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