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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>GETSEC[SEXIT]
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— Exit Measured Environment</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>GETSEC[SEXIT]
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— Exit Measured Environment</h1>
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<table>
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<tr>
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<th>Opcode</th>
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<th>Instruction</th>
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<th>Description</th></tr>
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<tr>
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<td>NP 0F 37 (EAX=5)</td>
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<td>GETSEC[SEXIT]</td>
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<td>Exit measured environment.</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>The GETSEC[SEXIT] instruction initiates an exit of a measured environment established by GETSEC[SENTER]. The SEXIT leaf of GETSEC is selected with EAX set to 5 at execution. This instruction leaf sends a message to all logical processors in the platform to signal the measured environment exit.</p>
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<p>There are restrictions enforced by the processor for the execution of the GETSEC[SEXIT] instruction:</p>
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<ul>
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<li>Execution is not allowed unless the processor is in protected mode (CR0.PE = 1) with CPL = 0 and EFLAGS.VM = 0.</li>
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<li>The processor must be in a measured environment as launched by a previous GETSEC[SENTER] instruction, but not still in authenticated code execution mode.</li>
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<li>To avoid potential interoperability conflicts between modes, the processor is not allowed to execute this instruction if it currently is in SMM or in VMX operation.</li>
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<li>To ensure consistent handling of SIPI messages, the processor executing the GETSEC[SEXIT] instruction must also be designated the BSP (bootstrap processor) as defined by the register bit IA32_APIC_BASE.BSP (bit 8).</li></ul>
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<p>Failure to abide by the above conditions results in the processor signaling a general protection violation.</p>
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<p>This instruction initiates a sequence to rendezvous the RLPs with the ILP. It then clears the internal processor flag indicating the processor is operating in a measured environment.</p>
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<p>In response to a message signaling the completion of rendezvous, all RLPs restart execution with the instruction that was to be executed at the time GETSEC[SEXIT] was recognized. This applies to all processor conditions, with the following exceptions:</p>
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<ul>
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<li>If an RLP executed HLT and was in this halt state at the time of the message initiated by GETSEC[SEXIT], then execution resumes in the halt state.</li>
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<li>If an RLP was executing MWAIT, then a message initiated by GETSEC[SEXIT] causes an exit of the MWAIT state, falling through to the next instruction.</li>
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<li>If an RLP was executing an intermediate iteration of a string instruction, then the processor resumes execution of the string instruction at the point which the message initiated by GETSEC[SEXIT] was recognized.</li>
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<li>If an RLP is still in the SENTER sleep state (never awakened with GETSEC[WAKEUP]), it will be sent to the wait-for-SIPI state after first clearing the bootstrap processor indicator flag (IA32_APIC_BASE.BSP) and any pending SIPI state. In this case, such RLPs are initialized to an architectural state consistent with having taken a soft reset using the INIT# pin.</li></ul>
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<p>Prior to completion of the GETSEC[SEXIT] operation, both the ILP and any active RLPs unmask the response of the external event signals INIT#, A20M, NMI#, and SMI#. This unmasking is performed unconditionally to recognize pin events which are masked after a GETSEC[SENTER]. The state of A20M is unmasked, as the A20M pin is not recognized while the measured environment is active.</p>
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<p>On a successful exit of the measured environment, the ILP re-locks the Intel® TXT-capable chipset private configuration space. GETSEC[SEXIT] does not affect the content of any PCR.</p>
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<p>At completion of GETSEC[SEXIT] by the ILP, execution proceeds to the next instruction. Since EFLAGS and the debug register state are not modified by this instruction, a pending trap condition is free to be signaled if previously enabled.</p>
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<h2 id="operation-in-a-uni-processor-platform">Operation in a Uni-Processor Platform<a class="anchor" href="#operation-in-a-uni-processor-platform">
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¶
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</a></h2>
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<p>(* The state of the internal flag ACMODEFLAG and SENTERFLAG persist across instruction boundary *)</p>
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<p><strong>GETSEC[SEXIT] (ILP Only):</strong></p>
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<p>IF (CR4.SMXE=0)</p>
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<p>THEN #UD;</p>
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<p>ELSE IF (in VMX non-root operation)</p>
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<p>THEN VM Exit (reason=”GETSEC instruction”);</p>
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<p>ELSE IF (GETSEC leaf unsupported)</p>
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<p>THEN #UD;</p>
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<p>ELSE IF ((in VMX root operation) or</p>
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<p>(CR0.PE=0) or (CPL>0) or (EFLAGS.VM=1) or</p>
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<p>(IA32_APIC_BASE.BSP=0) or</p>
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<p>(TXT chipset not present) or</p>
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<p>(SENTERFLAG=0) or (ACMODEFLAG=1) or (IN_SMM=1))</p>
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<p>THEN #GP(0);</p>
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<p>SignalTXTMsg(SEXIT);</p>
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<p>DO</p>
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<p>WHILE (no SignalSEXIT message);</p>
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<p><strong>TXT_SEXIT_MSG_EVENT (ILP & RLP):</strong></p>
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<p>Mask and clear SignalSEXIT event;</p>
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<p>Clear MONITOR FSM;</p>
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<p>Unmask SignalSENTER event;</p>
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<p>IF (in VMX operation)</p>
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<p>THEN TXT-SHUTDOWN(#IllegalEvent);</p>
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<p>SignalTXTMsg(SEXITAck);</p>
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<p>IF (logical processor is not ILP)</p>
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<p>THEN GOTO RLP_SEXIT_ROUTINE;</p>
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<p>(* ILP waits for all logical processors to ACK *)</p>
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<p>DO</p>
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<p>DONE := READ(LT.STS);</p>
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<p>WHILE (NOT DONE);</p>
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<p>SignalTXTMsg(SEXITContinue);</p>
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<p>SignalTXTMsg(ClosePrivate);</p>
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<p>SENTERFLAG := 0;</p>
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<p>Unmask SMI, INIT, A20M, and NMI external pin events;</p>
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<p>END;</p>
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<p><strong>RLP_SEXIT_ROUTINE (RLPs Only):</strong></p>
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<p>Wait for SignalSEXITContinue message;</p>
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<p>Unmask SMI, INIT, A20M, and NMI external pin events;</p>
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<p>IF (prior execution state = HLT)</p>
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<p>THEN reenter HLT state;</p>
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<p>IF (prior execution state = SENTER sleep)</p>
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<p>THEN</p>
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<p>IA32_APIC_BASE.BSP := 0;</p>
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<p>Clear pending SIPI state;</p>
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<p>Call INIT_PROCESSOR_STATE;</p>
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<p>Unmask SIPI event;</p>
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<p>GOTO WAIT-FOR-SIPI;</p>
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<p>FI;</p>
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<p>END;</p>
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<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
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¶
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</a></h2>
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<p>ILP: None.</p>
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<p>RLPs: All flags are modified for an RLP. returning to wait-for-SIPI state, none otherwise.</p>
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<h2 id="use-of-prefixes">Use of Prefixes<a class="anchor" href="#use-of-prefixes">
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¶
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</a></h2>
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<p>LOCK Causes #UD.</p>
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<p>REP* Cause #UD (includes REPNE/REPNZ and REP/REPE/REPZ).</p>
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<p>Operand size Causes #UD.</p>
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<p>NP 66/F2/F3 prefixes are not allowed.</p>
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<p>Segmentoverrides Ignored.</p>
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<p>Address size Ignored.</p>
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<p>REX Ignored.</p>
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<h2 class="exceptions" id="protected-mode-exceptions">Protected Mode Exceptions<a class="anchor" href="#protected-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td rowspan="2">#UD</td>
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<td>If CR4.SMXE = 0.</td></tr>
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<tr>
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<td>If GETSEC[SEXIT] is not reported as supported by GETSEC[CAPABILITIES].</td></tr>
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<tr>
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<td rowspan="6">#GP(0)</td>
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<td>If CR0.PE = 0 or CPL > 0 or EFLAGS.VM = 1.</td></tr>
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<tr>
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<td>If in VMX root operation.</td></tr>
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<tr>
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<td>If the initiating processor is not designated via the MSR bit IA32_APIC_BASE.BSP.</td></tr>
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<tr>
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<td>If an Intel® TXT-capable chipset is not present.</td></tr>
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<tr>
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<td>If a protected partition is not already active or the processor is already in authenticated code mode.</td></tr>
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<tr>
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<td>If the processor is in SMM.</td></tr></table>
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<h2 class="exceptions" id="real-address-mode-exceptions">Real-Address Mode Exceptions<a class="anchor" href="#real-address-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td rowspan="2">#UD</td>
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<td>If CR4.SMXE = 0.</td></tr>
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<tr>
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<td>If GETSEC[SEXIT] is not reported as supported by GETSEC[CAPABILITIES].</td></tr>
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<tr>
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<td>#GP(0)</td>
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<td>GETSEC[SEXIT] is not recognized in real-address mode.</td></tr></table>
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<h2 class="exceptions" id="virtual-8086-mode-exceptions">Virtual-8086 Mode Exceptions<a class="anchor" href="#virtual-8086-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td rowspan="2">#UD</td>
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<td>If CR4.SMXE = 0.</td></tr>
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<tr>
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<td>If GETSEC[SEXIT] is not reported as supported by GETSEC[CAPABILITIES].</td></tr>
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<tr>
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<td>#GP(0)</td>
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<td>GETSEC[SEXIT] is not recognized in virtual-8086 mode.</td></tr></table>
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<h2 class="exceptions" id="compatibility-mode-exceptions">Compatibility Mode Exceptions<a class="anchor" href="#compatibility-mode-exceptions">
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¶
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</a></h2>
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<p>All protected mode exceptions apply.</p>
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<h2 class="exceptions" id="64-bit-mode-exceptions">64-Bit Mode Exceptions<a class="anchor" href="#64-bit-mode-exceptions">
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¶
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</a></h2>
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<p>All protected mode exceptions apply.</p>
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<h2 id="vm-exit-condition">VM-Exit Condition<a class="anchor" href="#vm-exit-condition">
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¶
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</a></h2>
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<p>Reason (GETSEC) If in VMX non-root operation.</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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