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114 lines
6.6 KiB
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>RSQRTPS
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— Compute Reciprocals of Square Roots of Packed Single Precision Floating-PointValues</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>RSQRTPS
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— Compute Reciprocals of Square Roots of Packed Single Precision Floating-PointValues</h1>
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<table>
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<tr>
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<th>Opcode*/Instruction</th>
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<th>Op/En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>NP 0F 52 /r RSQRTPS xmm1, xmm2/m128</td>
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<td>RM</td>
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<td>V/V</td>
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<td>SSE</td>
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<td>Computes the approximate reciprocals of the square roots of the packed single precision floating-point values in xmm2/m128 and stores the results in xmm1.</td></tr>
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<tr>
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<td>VEX.128.0F.WIG 52 /r VRSQRTPS xmm1, xmm2/m128</td>
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<td>RM</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Computes the approximate reciprocals of the square roots of packed single precision values in xmm2/mem and stores the results in xmm1.</td></tr>
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<tr>
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<td>VEX.256.0F.WIG 52 /r VRSQRTPS ymm1, ymm2/m256</td>
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<td>RM</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Computes the approximate reciprocals of the square roots of packed single precision values in ymm2/mem and stores the results in ymm1.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>RM</td>
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<td>ModRM:reg (w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Performs a SIMD computation of the approximate reciprocals of the square roots of the four packed single precision floating-point values in the source operand (second operand) and stores the packed single precision floating-point results in the destination operand. The source operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM register. See <span class="not-imported">Figure 10-5</span> in the Intel<sup>®</sup> 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for an illustration of a SIMD single precision floating-point operation.</p>
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<p>The relative error for this approximation is:</p>
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<p>|Relative Error| ≤ 1.5 ∗ 2<sup>−12</sup></p>
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<p>The RSQRTPS instruction is not affected by the rounding control bits in the MXCSR register. When a source value is a 0.0, an ∞ of the sign of the source value is returned. A denormal source value is treated as a 0.0 (of the same sign). When a source value is a negative value (other than −0.0), a floating-point indefinite is returned. When a source value is an SNaN or QNaN, the SNaN is converted to a QNaN or the source QNaN is returned.</p>
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<p>In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).</p>
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<p>128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding YMM register destination are unmodified.</p>
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<p>VEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding YMM register destination are zeroed.</p>
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<p>VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM register or a 256-bit memory location. The destination operand is a YMM register.</p>
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<p>Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<h3 id="rsqrtps--128-bit-legacy-sse-version-">RSQRTPS (128-bit Legacy SSE Version)<a class="anchor" href="#rsqrtps--128-bit-legacy-sse-version-">
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¶
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</a></h3>
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<pre>DEST[31:0] := APPROXIMATE(1/SQRT(SRC[31:0]))
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DEST[63:32] := APPROXIMATE(1/SQRT(SRC1[63:32]))
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DEST[95:64] := APPROXIMATE(1/SQRT(SRC1[95:64]))
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DEST[127:96] := APPROXIMATE(1/SQRT(SRC2[127:96]))
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DEST[MAXVL-1:128] (Unmodified)
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</pre>
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<h3 id="vrsqrtps--vex-128-encoded-version-">VRSQRTPS (VEX.128 Encoded Version)<a class="anchor" href="#vrsqrtps--vex-128-encoded-version-">
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¶
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</a></h3>
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<pre>DEST[31:0] := APPROXIMATE(1/SQRT(SRC[31:0]))
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DEST[63:32] := APPROXIMATE(1/SQRT(SRC1[63:32]))
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DEST[95:64] := APPROXIMATE(1/SQRT(SRC1[95:64]))
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DEST[127:96] := APPROXIMATE(1/SQRT(SRC2[127:96]))
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DEST[MAXVL-1:128] := 0
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</pre>
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<h3 id="vrsqrtps--vex-256-encoded-version-">VRSQRTPS (VEX.256 Encoded Version)<a class="anchor" href="#vrsqrtps--vex-256-encoded-version-">
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¶
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</a></h3>
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<pre>DEST[31:0] := APPROXIMATE(1/SQRT(SRC[31:0]))
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DEST[63:32] := APPROXIMATE(1/SQRT(SRC1[63:32]))
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DEST[95:64] := APPROXIMATE(1/SQRT(SRC1[95:64]))
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DEST[127:96] := APPROXIMATE(1/SQRT(SRC2[127:96]))
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DEST[159:128] := APPROXIMATE(1/SQRT(SRC2[159:128]))
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DEST[191:160] := APPROXIMATE(1/SQRT(SRC2[191:160]))
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DEST[223:192] := APPROXIMATE(1/SQRT(SRC2[223:192]))
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DEST[255:224] := APPROXIMATE(1/SQRT(SRC2[255:224]))
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</pre>
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<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h2>
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<pre>RSQRTPS __m128 _mm_rsqrt_ps(__m128 a)
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</pre>
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<pre>RSQRTPS __m256 _mm256_rsqrt_ps (__m256 a);
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</pre>
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<h2 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h2>
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<p>See <span class="not-imported">Table 2-21</span>, “Type 4 Class Exception Conditions,” additionally:</p>
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<table>
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<tr>
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<td>#UD</td>
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<td>If VEX.vvvv ≠ 1111B.</td></tr></table><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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