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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>PXOR
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— Logical Exclusive OR</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>PXOR
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— Logical Exclusive OR</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>NP 0F EF /r<sup>1</sup> PXOR mm, mm/m64</td>
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<td>A</td>
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<td>V/V</td>
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<td>MMX</td>
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<td>Bitwise XOR of mm/m64 and mm.</td></tr>
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<tr>
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<td>66 0F EF /r PXOR xmm1, xmm2/m128</td>
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<td>A</td>
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<td>V/V</td>
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<td>SSE2</td>
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<td>Bitwise XOR of xmm2/m128 and xmm1.</td></tr>
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<tr>
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<td>VEX.128.66.0F.WIG EF /r VPXOR xmm1, xmm2, xmm3/m128</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Bitwise XOR of xmm3/m128 and xmm2.</td></tr>
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<tr>
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<td>VEX.256.66.0F.WIG EF /r VPXOR ymm1, ymm2, ymm3/m256</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX2</td>
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<td>Bitwise XOR of ymm3/m256 and ymm2.</td></tr>
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<tr>
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<td>EVEX.128.66.0F.W0 EF /r VPXORD xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst</td>
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<td>C</td>
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<td>V/V</td>
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<td>AVX512VL AVX512F</td>
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<td>Bitwise XOR of packed doubleword integers in xmm2 and xmm3/m128 using writemask k1.</td></tr>
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<tr>
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<td>EVEX.256.66.0F.W0 EF /r VPXORD ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst</td>
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<td>C</td>
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<td>V/V</td>
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<td>AVX512VL AVX512F</td>
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<td>Bitwise XOR of packed doubleword integers in ymm2 and ymm3/m256 using writemask k1.</td></tr>
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<tr>
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<td>EVEX.512.66.0F.W0 EF /r VPXORD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst</td>
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<td>C</td>
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<td>V/V</td>
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<td>AVX512F</td>
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<td>Bitwise XOR of packed doubleword integers in zmm2 and zmm3/m512/m32bcst using writemask k1.</td></tr>
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<tr>
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<td>EVEX.128.66.0F.W1 EF /r VPXORQ xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst</td>
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<td>C</td>
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<td>V/V</td>
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<td>AVX512VL AVX512F</td>
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<td>Bitwise XOR of packed quadword integers in xmm2 and xmm3/m128 using writemask k1.</td></tr>
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<tr>
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<td>EVEX.256.66.0F.W1 EF /r VPXORQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst</td>
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<td>C</td>
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<td>V/V</td>
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<td>AVX512VL AVX512F</td>
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<td>Bitwise XOR of packed quadword integers in ymm2 and ymm3/m256 using writemask k1.</td></tr>
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<tr>
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<td>EVEX.512.66.0F.W1 EF /r VPXORQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst</td>
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<td>C</td>
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<td>V/V</td>
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<td>AVX512F</td>
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<td>Bitwise XOR of packed quadword integers in zmm2 and zmm3/m512/m64bcst using writemask k1.</td></tr></table>
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<blockquote>
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<p>1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Classification,” in the Intel<sup>®</sup> 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A, and Section 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers,” in the Intel<sup>®</sup> 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.</p></blockquote>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple Type</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>N/A</td>
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<td>ModRM:reg (r, w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr>
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<tr>
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<td>B</td>
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<td>N/A</td>
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<td>ModRM:reg (w)</td>
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<td>VEX.vvvv (r)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td></tr>
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<tr>
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<td>C</td>
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<td>Full</td>
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<td>ModRM:reg (w)</td>
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<td>EVEX.vvvv (r)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Performs a bitwise logical exclusive-OR (XOR) operation on the source operand (second operand) and the destination operand (first operand) and stores the result in the destination operand. Each bit of the result is 1 if the corresponding bits of the two operands are different; each bit is 0 if the corresponding bits of the operands are the same.</p>
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<p>In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).</p>
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<p>Legacy SSE instructions 64-bit operand: The source operand can be an MMX technology register or a 64-bit memory location. The destination operand is an MMX technology register.</p>
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<p>128-bit Legacy SSE version: The second source operand is an XMM register or a 128-bit memory location. The first source operand and destination operands are XMM registers. Bits (MAXVL-1:128) of the corresponding YMM destination register remain unchanged.</p>
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<p>VEX.128 encoded version: The second source operand is an XMM register or a 128-bit memory location. The first source operand and destination operands are XMM registers. Bits (MAXVL-1:128) of the destination YMM register are zeroed.</p>
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<p>VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAXVL-1:256) of the corresponding register destination are zeroed.</p>
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<p>EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with write-mask k1.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<h3 id="pxor--64-bit-operand-">PXOR (64-bit Operand)<a class="anchor" href="#pxor--64-bit-operand-">
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¶
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</a></h3>
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<pre>DEST := DEST XOR SRC
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</pre>
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<h3 id="pxor--128-bit-legacy-sse-version-">PXOR (128-bit Legacy SSE Version)<a class="anchor" href="#pxor--128-bit-legacy-sse-version-">
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¶
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</a></h3>
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<pre>DEST := DEST XOR SRC
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DEST[MAXVL-1:128] (Unmodified)
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</pre>
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<h3 id="vpxor--vex-128-encoded-version-">VPXOR (VEX.128 Encoded Version)<a class="anchor" href="#vpxor--vex-128-encoded-version-">
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¶
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</a></h3>
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<pre>DEST := SRC1 XOR SRC2
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DEST[MAXVL-1:128] := 0
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</pre>
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<h3 id="vpxor--vex-256-encoded-version-">VPXOR (VEX.256 Encoded Version)<a class="anchor" href="#vpxor--vex-256-encoded-version-">
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¶
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</a></h3>
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<pre>DEST := SRC1 XOR SRC2
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DEST[MAXVL-1:256] := 0
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</pre>
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<h3 id="vpxord--evex-encoded-versions-">VPXORD (EVEX Encoded Versions)<a class="anchor" href="#vpxord--evex-encoded-versions-">
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¶
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</a></h3>
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<pre>(KL, VL) = (4, 128), (8, 256), (16, 512)
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FOR j := 0 TO KL-1
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i := j * 32
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IF k1[j] OR *no writemask* THEN
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IF (EVEX.b = 1) AND (SRC2 *is memory*)
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THEN DEST[i+31:i] := SRC1[i+31:i] BITWISE XOR SRC2[31:0]
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ELSE DEST[i+31:i] := SRC1[i+31:i] BITWISE XOR SRC2[i+31:i]
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FI;
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ELSE
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IF *merging-masking* ; merging-masking
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THEN *DEST[31:0] remains unchanged*
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ELSE
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; zeroing-masking
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DEST[31:0] := 0
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FI;
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FI;
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ENDFOR;
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DEST[MAXVL-1:VL] := 0
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</pre>
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<h3 id="vpxorq--evex-encoded-versions-">VPXORQ (EVEX Encoded Versions)<a class="anchor" href="#vpxorq--evex-encoded-versions-">
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¶
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</a></h3>
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<pre>(KL, VL) = (2, 128), (4, 256), (8, 512)
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FOR j := 0 TO KL-1
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i := j * 64
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IF k1[j] OR *no writemask* THEN
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IF (EVEX.b = 1) AND (SRC2 *is memory*)
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THEN DEST[i+63:i] := SRC1[i+63:i] BITWISE XOR SRC2[63:0]
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ELSE DEST[i+63:i] := SRC1[i+63:i] BITWISE XOR SRC2[i+63:i]
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FI;
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ELSE
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IF *merging-masking* ; merging-masking
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THEN *DEST[63:0] remains unchanged*
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ELSE ; zeroing-masking
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DEST[63:0] := 0
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FI;
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FI;
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ENDFOR;
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DEST[MAXVL-1:VL] := 0
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</pre>
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<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h2>
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<pre>VPXORD __m512i _mm512_xor_epi32(__m512i a, __m512i b)
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</pre>
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<pre>VPXORD __m512i _mm512_mask_xor_epi32(__m512i s, __mmask16 m, __m512i a, __m512i b)
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</pre>
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<pre>VPXORD __m512i _mm512_maskz_xor_epi32( __mmask16 m, __m512i a, __m512i b)
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</pre>
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<pre>VPXORD __m256i _mm256_xor_epi32(__m256i a, __m256i b)
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</pre>
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<pre>VPXORD __m256i _mm256_mask_xor_epi32(__m256i s, __mmask8 m, __m256i a, __m256i b)
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</pre>
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<pre>VPXORD __m256i _mm256_maskz_xor_epi32( __mmask8 m, __m256i a, __m256i b)
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</pre>
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<pre>VPXORD __m128i _mm_xor_epi32(__m128i a, __m128i b)
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</pre>
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<pre>VPXORD __m128i _mm_mask_xor_epi32(__m128i s, __mmask8 m, __m128i a, __m128i b)
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</pre>
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<pre>VPXORD __m128i _mm_maskz_xor_epi32( __mmask16 m, __m128i a, __m128i b)
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</pre>
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<pre>VPXORQ __m512i _mm512_xor_epi64( __m512i a, __m512i b);
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</pre>
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<pre>VPXORQ __m512i _mm512_mask_xor_epi64(__m512i s, __mmask8 m, __m512i a, __m512i b);
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</pre>
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<pre>VPXORQ __m512i _mm512_maskz_xor_epi64(__mmask8 m, __m512i a, __m512i b);
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</pre>
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<pre>VPXORQ __m256i _mm256_xor_epi64( __m256i a, __m256i b);
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</pre>
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<pre>VPXORQ __m256i _mm256_mask_xor_epi64(__m256i s, __mmask8 m, __m256i a, __m256i b);
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</pre>
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<pre>VPXORQ __m256i _mm256_maskz_xor_epi64(__mmask8 m, __m256i a, __m256i b);
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</pre>
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<pre>VPXORQ __m128i _mm_xor_epi64( __m128i a, __m128i b);
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</pre>
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<pre>VPXORQ __m128i _mm_mask_xor_epi64(__m128i s, __mmask8 m, __m128i a, __m128i b);
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</pre>
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<pre>VPXORQ __m128i _mm_maskz_xor_epi64(__mmask8 m, __m128i a, __m128i b);
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</pre>
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<pre>PXOR:__m64 _mm_xor_si64 (__m64 m1, __m64 m2)
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</pre>
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<pre>(V)PXOR:__m128i _mm_xor_si128 ( __m128i a, __m128i b)
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</pre>
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<pre>VPXOR:__m256i _mm256_xor_si256 ( __m256i a, __m256i b)
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</pre>
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<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="numeric-exceptions">Numeric Exceptions<a class="anchor" href="#numeric-exceptions">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h2>
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<p>Non-EVEX-encoded instruction, see <span class="not-imported">Table 2-21</span>, “Type 4 Class Exception Conditions.”</p>
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<p>EVEX-encoded instruction, see <span class="not-imported">Table 2-49</span>, “Type E4 Class Exception Conditions.”</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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