forked from NRZCode/ia32-64
106 lines
4.7 KiB
HTML
106 lines
4.7 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>PHMINPOSUW
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— Packed Horizontal Word Minimum</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>PHMINPOSUW
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— Packed Horizontal Word Minimum</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>66 0F 38 41 /r PHMINPOSUW xmm1, xmm2/m128</td>
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<td>RM</td>
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<td>V/V</td>
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<td>SSE4_1</td>
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<td>Find the minimum unsigned word in xmm2/m128 and place its value in the low word of xmm1 and its index in the second-lowest word of xmm1.</td></tr>
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<tr>
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<td>VEX.128.66.0F38.WIG 41 /r VPHMINPOSUW xmm1, xmm2/m128</td>
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<td>RM</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Find the minimum unsigned word in xmm2/m128 and place its value in the low word of xmm1 and its index in the second-lowest word of xmm1.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>RM</td>
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<td>ModRM:reg (w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Determine the minimum unsigned word value in the source operand (second operand) and place the unsigned word in the low word (bits 0-15) of the destination operand (first operand). The word index of the minimum value is stored in bits 16-18 of the destination operand. The remaining upper bits of the destination are set to zero.</p>
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<p>128-bit Legacy SSE version: Bits (MAXVL-1:128) of the corresponding XMM destination register remain unchanged.</p>
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<p>VEX.128 encoded version: Bits (MAXVL-1:128) of the destination XMM register are zeroed. VEX.vvvv is reserved and must be 1111b, VEX.L must be 0, otherwise the instruction will #UD.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<h3 id="phminposuw--128-bit-legacy-sse-version-">PHMINPOSUW (128-bit Legacy SSE Version)<a class="anchor" href="#phminposuw--128-bit-legacy-sse-version-">
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¶
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</a></h3>
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<pre>INDEX := 0;
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MIN := SRC[15:0]
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IF (SRC[31:16] < MIN)
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THEN INDEX := 1; MIN := SRC[31:16]; FI;
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IF (SRC[47:32] < MIN)
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THEN INDEX := 2; MIN := SRC[47:32]; FI;
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* Repeat operation for words 3 through 6
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IF (SRC[127:112] < MIN)
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THEN INDEX := 7; MIN := SRC[127:112]; FI;
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DEST[15:0] := MIN;
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DEST[18:16] := INDEX;
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DEST[127:19] := 0000000000000000000000000000H;
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</pre>
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<h3 id="vphminposuw--vex-128-encoded-version-">VPHMINPOSUW (VEX.128 Encoded Version)<a class="anchor" href="#vphminposuw--vex-128-encoded-version-">
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¶
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</a></h3>
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<pre>INDEX := 0
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MIN := SRC[15:0]
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IF (SRC[31:16] < MIN) THEN INDEX := 1; MIN := SRC[31:16]
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IF (SRC[47:32] < MIN) THEN INDEX := 2; MIN := SRC[47:32]
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* Repeat operation for words 3 through 6
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IF (SRC[127:112] < MIN) THEN INDEX := 7; MIN := SRC[127:112]
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DEST[15:0] := MIN
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DEST[18:16] := INDEX
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DEST[127:19] := 0000000000000000000000000000H
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DEST[MAXVL-1:128] := 0
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</pre>
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<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h2>
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<pre>PHMINPOSUW __m128i _mm_minpos_epu16( __m128i packed_words);
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</pre>
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<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h2>
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<p>See <span class="not-imported">Table 2-21</span>, “Type 4 Class Exception Conditions,” additionally:</p>
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<table>
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<tr>
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<td rowspan="2">#UD</td>
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<td>If VEX.L = 1.</td></tr>
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<tr>
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<td>If VEX.vvvv ≠ 1111B.</td></tr></table><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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