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453 lines
19 KiB
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<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>PCMPEQB/PCMPEQW/PCMPEQD
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— Compare Packed Data for Equal</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>PCMPEQB/PCMPEQW/PCMPEQD
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— Compare Packed Data for Equal</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/ En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>NP 0F 74 /r<sup>1</sup> PCMPEQB mm, mm/m64</td>
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<td>A</td>
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<td>V/V</td>
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<td>MMX</td>
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<td>Compare packed bytes in mm/m64 and mm for equality.</td></tr>
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<tr>
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<td>66 0F 74 /r PCMPEQB xmm1, xmm2/m128</td>
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<td>A</td>
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<td>V/V</td>
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<td>SSE2</td>
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<td>Compare packed bytes in xmm2/m128 and xmm1 for equality.</td></tr>
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<tr>
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<td>NP 0F 75 /r<sup>1</sup> PCMPEQW mm, mm/m64</td>
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<td>A</td>
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<td>V/V</td>
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<td>MMX</td>
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<td>Compare packed words in mm/m64 and mm for equality.</td></tr>
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<tr>
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<td>66 0F 75 /r PCMPEQW xmm1, xmm2/m128</td>
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<td>A</td>
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<td>V/V</td>
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<td>SSE2</td>
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<td>Compare packed words in xmm2/m128 and xmm1 for equality.</td></tr>
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<tr>
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<td>NP 0F 76 /r<sup>1</sup> PCMPEQD mm, mm/m64</td>
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<td>A</td>
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<td>V/V</td>
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<td>MMX</td>
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<td>Compare packed doublewords in mm/m64 and mm for equality.</td></tr>
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<tr>
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<td>66 0F 76 /r PCMPEQD xmm1, xmm2/m128</td>
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<td>A</td>
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<td>V/V</td>
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<td>SSE2</td>
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<td>Compare packed doublewords in xmm2/m128 and xmm1 for equality.</td></tr>
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<tr>
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<td>VEX.128.66.0F.WIG 74 /r VPCMPEQB xmm1, xmm2, xmm3/m128</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Compare packed bytes in xmm3/m128 and xmm2 for equality.</td></tr>
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<tr>
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<td>VEX.128.66.0F.WIG 75 /r VPCMPEQW xmm1, xmm2, xmm3/m128</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Compare packed words in xmm3/m128 and xmm2 for equality.</td></tr>
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<tr>
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<td>VEX.128.66.0F.WIG 76 /r VPCMPEQD xmm1, xmm2, xmm3/m128</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Compare packed doublewords in xmm3/m128 and xmm2 for equality.</td></tr>
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<tr>
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<td>VEX.256.66.0F.WIG 74 /r VPCMPEQB ymm1, ymm2, ymm3 /m256</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX2</td>
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<td>Compare packed bytes in ymm3/m256 and ymm2 for equality.</td></tr>
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<tr>
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<td>VEX.256.66.0F.WIG 75 /r VPCMPEQW ymm1, ymm2, ymm3 /m256</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX2</td>
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<td>Compare packed words in ymm3/m256 and ymm2 for equality.</td></tr>
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<tr>
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<td>VEX.256.66.0F.WIG 76 /r VPCMPEQD ymm1, ymm2, ymm3 /m256</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX2</td>
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<td>Compare packed doublewords in ymm3/m256 and ymm2 for equality.</td></tr>
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<tr>
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<td>EVEX.128.66.0F.W0 76 /r VPCMPEQD k1 {k2}, xmm2, xmm3/m128/m32bcst</td>
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<td>C</td>
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<td>V/V</td>
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<td>AVX512VL AVX512F</td>
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<td>Compare Equal between int32 vector xmm2 and int32 vector xmm3/m128/m32bcst, and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask.</td></tr>
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<tr>
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<td>EVEX.256.66.0F.W0 76 /r VPCMPEQD k1 {k2}, ymm2, ymm3/m256/m32bcst</td>
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<td>C</td>
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<td>V/V</td>
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<td>AVX512VL AVX512F</td>
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<td>Compare Equal between int32 vector ymm2 and int32 vector ymm3/m256/m32bcst, and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask.</td></tr>
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<tr>
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<td>EVEX.512.66.0F.W0 76 /r VPCMPEQD k1 {k2}, zmm2, zmm3/m512/m32bcst</td>
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<td>C</td>
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<td>V/V</td>
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<td>AVX512F</td>
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<td>Compare Equal between int32 vectors in zmm2 and zmm3/m512/m32bcst, and set destination k1 according to the comparison results under writemask k2.</td></tr>
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<tr>
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<td>EVEX.128.66.0F.WIG 74 /r VPCMPEQB k1 {k2}, xmm2, xmm3 /m128</td>
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<td>D</td>
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<td>V/V</td>
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<td>AVX512VL AVX512BW</td>
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<td>Compare packed bytes in xmm3/m128 and xmm2 for equality and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask.</td></tr>
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<tr>
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<td>EVEX.256.66.0F.WIG 74 /r VPCMPEQB k1 {k2}, ymm2, ymm3 /m256</td>
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<td>D</td>
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<td>V/V</td>
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<td>AVX512VL AVX512BW</td>
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<td>Compare packed bytes in ymm3/m256 and ymm2 for equality and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask.</td></tr>
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<tr>
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<td>EVEX.512.66.0F.WIG 74 /r VPCMPEQB k1 {k2}, zmm2, zmm3 /m512</td>
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<td>D</td>
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<td>V/V</td>
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<td>AVX512BW</td>
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<td>Compare packed bytes in zmm3/m512 and zmm2 for equality and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask.</td></tr>
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<tr>
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<td>EVEX.128.66.0F.WIG 75 /r VPCMPEQW k1 {k2}, xmm2, xmm3 /m128</td>
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<td>D</td>
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<td>V/V</td>
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<td>AVX512VL AVX512BW</td>
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<td>Compare packed words in xmm3/m128 and xmm2 for equality and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask.</td></tr>
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<tr>
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<td>EVEX.256.66.0F.WIG 75 /r VPCMPEQW k1 {k2}, ymm2, ymm3 /m256</td>
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<td>D</td>
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<td>V/V</td>
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<td>AVX512VL AVX512BW</td>
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<td>Compare packed words in ymm3/m256 and ymm2 for equality and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask.</td></tr>
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<tr>
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<td>EVEX.512.66.0F.WIG 75 /r VPCMPEQW k1 {k2}, zmm2, zmm3 /m512</td>
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<td>D</td>
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<td>V/V</td>
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<td>AVX512BW</td>
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<td>Compare packed words in zmm3/m512 and zmm2 for equality and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask.</td></tr></table>
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<blockquote>
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<p>1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Classification,” in the Intel<sup>®</sup> 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A, and Section 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers,” in the Intel<sup>®</sup> 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.</p></blockquote>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple Type</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>N/A</td>
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<td>ModRM:reg (r, w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr>
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<tr>
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<td>B</td>
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<td>N/A</td>
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<td>ModRM:reg (w)</td>
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<td>VEX.vvvv (r)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td></tr>
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<tr>
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<td>C</td>
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<td>Full</td>
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<td>ModRM:reg (w)</td>
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<td>EVEX.vvvv (r)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td></tr>
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<tr>
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<td>D</td>
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<td>Full Mem</td>
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<td>ModRM:reg (w)</td>
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<td>EVEX.vvvv (r)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Performs a SIMD compare for equality of the packed bytes, words, or doublewords in the destination operand (first operand) and the source operand (second operand). If a pair of data elements is equal, the corresponding data element in the destination operand is set to all 1s; otherwise, it is set to all 0s.</p>
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<p>The (V)PCMPEQB instruction compares the corresponding bytes in the destination and source operands; the (V)PCMPEQW instruction compares the corresponding words in the destination and source operands; and the (V)PCMPEQD instruction compares the corresponding doublewords in the destination and source operands.</p>
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<p>In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).</p>
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<p>Legacy SSE instructions: The source operand can be an MMX technology register or a 64-bit memory location. The destination operand can be an MMX technology register.</p>
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<p>128-bit Legacy SSE version: The second source operand can be an XMM register or a 128-bit memory location. The first source and destination operands are XMM registers. Bits (MAXVL-1:128) of the corresponding YMM destination register remain unchanged.</p>
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<p>VEX.128 encoded version: The second source operand can be an XMM register or a 128-bit memory location. The first source and destination operands are XMM registers. Bits (MAXVL-1:128) of the corresponding YMM register are zeroed.</p>
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<p>VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register or a 256-bit memory location. The destination operand is a YMM register.</p>
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<p>EVEX encoded VPCMPEQD: The first source operand (second operand) is a ZMM/YMM/XMM register. The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand (first operand) is a mask register updated according to the writemask k2.</p>
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<p>EVEX encoded VPCMPEQB/W: The first source operand (second operand) is a ZMM/YMM/XMM register. The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination operand (first operand) is a mask register updated according to the writemask k2.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<h3 id="pcmpeqb--with-64-bit-operands-">PCMPEQB (With 64-bit Operands)<a class="anchor" href="#pcmpeqb--with-64-bit-operands-">
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¶
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</a></h3>
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<pre>IF DEST[7:0] = SRC[7:0]
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THEN DEST[7:0) := FFH;
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ELSE DEST[7:0] := 0; FI;
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(* Continue comparison of 2nd through 7th bytes in DEST and SRC *)
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IF DEST[63:56] = SRC[63:56]
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THEN DEST[63:56] := FFH;
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ELSE DEST[63:56] := 0; FI;
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</pre>
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<h3 id="compare_bytes_equal--src1--src2-">COMPARE_BYTES_EQUAL (SRC1, SRC2)<a class="anchor" href="#compare_bytes_equal--src1--src2-">
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¶
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</a></h3>
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<pre> IF SRC1[7:0] = SRC2[7:0]
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THEN DEST[7:0] := FFH;
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ELSE DEST[7:0] := 0; FI;
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(* Continue comparison of 2nd through 15th bytes in SRC1 and SRC2 *)
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IF SRC1[127:120] = SRC2[127:120]
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THEN DEST[127:120] := FFH;
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ELSE DEST[127:120] := 0; FI;
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</pre>
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<h3 id="compare_words_equal--src1--src2-">COMPARE_WORDS_EQUAL (SRC1, SRC2)<a class="anchor" href="#compare_words_equal--src1--src2-">
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¶
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</a></h3>
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<pre> IF SRC1[15:0] = SRC2[15:0]
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THEN DEST[15:0] := FFFFH;
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ELSE DEST[15:0] := 0; FI;
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(* Continue comparison of 2nd through 7th 16-bit words in SRC1 and SRC2 *)
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IF SRC1[127:112] = SRC2[127:112]
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THEN DEST[127:112] := FFFFH;
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ELSE DEST[127:112] := 0; FI;
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</pre>
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<h3 id="compare_dwords_equal--src1--src2-">COMPARE_DWORDS_EQUAL (SRC1, SRC2)<a class="anchor" href="#compare_dwords_equal--src1--src2-">
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¶
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</a></h3>
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<pre> IF SRC1[31:0] = SRC2[31:0]
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THEN DEST[31:0] := FFFFFFFFH;
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ELSE DEST[31:0] := 0; FI;
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(* Continue comparison of 2nd through 3rd 32-bit dwords in SRC1 and SRC2 *)
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IF SRC1[127:96] = SRC2[127:96]
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THEN DEST[127:96] := FFFFFFFFH;
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ELSE DEST[127:96] := 0; FI;
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</pre>
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<h3 id="pcmpeqb--with-128-bit-operands-">PCMPEQB (With 128-bit Operands)<a class="anchor" href="#pcmpeqb--with-128-bit-operands-">
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¶
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</a></h3>
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<pre>DEST[127:0] := COMPARE_BYTES_EQUAL(DEST[127:0],SRC[127:0])
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DEST[MAXVL-1:128] (Unmodified)
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</pre>
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<h3 id="vpcmpeqb--vex-128-encoded-version-">VPCMPEQB (VEX.128 Encoded Version)<a class="anchor" href="#vpcmpeqb--vex-128-encoded-version-">
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¶
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</a></h3>
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<pre>DEST[127:0] := COMPARE_BYTES_EQUAL(SRC1[127:0],SRC2[127:0])
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DEST[MAXVL-1:128] := 0
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</pre>
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<h3 id="vpcmpeqb--vex-256-encoded-version-">VPCMPEQB (VEX.256 Encoded Version)<a class="anchor" href="#vpcmpeqb--vex-256-encoded-version-">
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¶
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</a></h3>
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<pre>DEST[127:0] := COMPARE_BYTES_EQUAL(SRC1[127:0],SRC2[127:0])
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DEST[255:128] := COMPARE_BYTES_EQUAL(SRC1[255:128],SRC2[255:128])
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DEST[MAXVL-1:256] := 0
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</pre>
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<h3 id="vpcmpeqb--evex-encoded-versions-">VPCMPEQB (EVEX Encoded Versions)<a class="anchor" href="#vpcmpeqb--evex-encoded-versions-">
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¶
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</a></h3>
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<pre>(KL, VL) = (16, 128), (32, 256), (64, 512)
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FOR j := 0 TO KL-1
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i := j * 8
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IF k2[j] OR *no writemask*
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THEN
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/* signed comparison */
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CMP := SRC1[i+7:i] == SRC2[i+7:i];
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IF CMP = TRUE
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THEN DEST[j] := 1;
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ELSE DEST[j] := 0; FI;
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ELSE DEST[j] := 0
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; zeroing-masking onlyFI;
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FI;
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ENDFOR
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DEST[MAX_KL-1:KL] := 0
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</pre>
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<h3 id="pcmpeqw--with-64-bit-operands-">PCMPEQW (With 64-bit Operands)<a class="anchor" href="#pcmpeqw--with-64-bit-operands-">
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¶
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</a></h3>
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<pre>IF DEST[15:0] = SRC[15:0]
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THEN DEST[15:0] := FFFFH;
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ELSE DEST[15:0] := 0; FI;
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(* Continue comparison of 2nd and 3rd words in DEST and SRC *)
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IF DEST[63:48] = SRC[63:48]
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THEN DEST[63:48] := FFFFH;
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ELSE DEST[63:48] := 0; FI;
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</pre>
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<h3 id="pcmpeqw--with-128-bit-operands-">PCMPEQW (With 128-bit Operands)<a class="anchor" href="#pcmpeqw--with-128-bit-operands-">
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¶
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</a></h3>
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<pre>DEST[127:0] := COMPARE_WORDS_EQUAL(DEST[127:0],SRC[127:0])
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DEST[MAXVL-1:128] (Unmodified)
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</pre>
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<h3 id="vpcmpeqw--vex-128-encoded-version-">VPCMPEQW (VEX.128 Encoded Version)<a class="anchor" href="#vpcmpeqw--vex-128-encoded-version-">
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¶
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</a></h3>
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<pre>DEST[127:0] := COMPARE_WORDS_EQUAL(SRC1[127:0],SRC2[127:0])
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DEST[MAXVL-1:128] := 0
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</pre>
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<h3 id="vpcmpeqw--vex-256-encoded-version-">VPCMPEQW (VEX.256 Encoded Version)<a class="anchor" href="#vpcmpeqw--vex-256-encoded-version-">
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¶
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</a></h3>
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<pre>DEST[127:0] := COMPARE_WORDS_EQUAL(SRC1[127:0],SRC2[127:0])
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DEST[255:128] := COMPARE_WORDS_EQUAL(SRC1[255:128],SRC2[255:128])
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DEST[MAXVL-1:256] := 0
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</pre>
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<h3 id="vpcmpeqw--evex-encoded-versions-">VPCMPEQW (EVEX Encoded Versions)<a class="anchor" href="#vpcmpeqw--evex-encoded-versions-">
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¶
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</a></h3>
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<pre>(KL, VL) = (8, 128), (16, 256), (32, 512)
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FOR j := 0 TO KL-1
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i := j * 16
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IF k2[j] OR *no writemask*
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THEN
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/* signed comparison */
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CMP := SRC1[i+15:i] == SRC2[i+15:i];
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IF CMP = TRUE
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THEN DEST[j] := 1;
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ELSE DEST[j] := 0; FI;
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ELSE DEST[j] := 0
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; zeroing-masking onlyFI;
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FI;
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ENDFOR
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DEST[MAX_KL-1:KL] := 0
|
||
</pre>
|
||
<h3 id="pcmpeqd--with-64-bit-operands-">PCMPEQD (With 64-bit Operands)<a class="anchor" href="#pcmpeqd--with-64-bit-operands-">
|
||
¶
|
||
</a></h3>
|
||
<pre>IF DEST[31:0] = SRC[31:0]
|
||
THEN DEST[31:0] := FFFFFFFFH;
|
||
ELSE DEST[31:0] := 0; FI;
|
||
IF DEST[63:32] = SRC[63:32]
|
||
THEN DEST[63:32] := FFFFFFFFH;
|
||
ELSE DEST[63:32] := 0; FI;
|
||
</pre>
|
||
<h3 id="pcmpeqd--with-128-bit-operands-">PCMPEQD (With 128-bit Operands)<a class="anchor" href="#pcmpeqd--with-128-bit-operands-">
|
||
¶
|
||
</a></h3>
|
||
<pre>DEST[127:0] := COMPARE_DWORDS_EQUAL(DEST[127:0],SRC[127:0])
|
||
DEST[MAXVL-1:128] (Unmodified)
|
||
</pre>
|
||
<h3 id="vpcmpeqd--vex-128-encoded-version-">VPCMPEQD (VEX.128 Encoded Version)<a class="anchor" href="#vpcmpeqd--vex-128-encoded-version-">
|
||
¶
|
||
</a></h3>
|
||
<pre>DEST[127:0] := COMPARE_DWORDS_EQUAL(SRC1[127:0],SRC2[127:0])
|
||
DEST[MAXVL-1:128] := 0
|
||
</pre>
|
||
<h3 id="vpcmpeqd--vex-256-encoded-version-">VPCMPEQD (VEX.256 Encoded Version)<a class="anchor" href="#vpcmpeqd--vex-256-encoded-version-">
|
||
¶
|
||
</a></h3>
|
||
<pre>DEST[127:0] := COMPARE_DWORDS_EQUAL(SRC1[127:0],SRC2[127:0])
|
||
DEST[255:128] := COMPARE_DWORDS_EQUAL(SRC1[255:128],SRC2[255:128])
|
||
DEST[MAXVL-1:256] := 0
|
||
</pre>
|
||
<h3 id="vpcmpeqd--evex-encoded-versions-">VPCMPEQD (EVEX Encoded Versions)<a class="anchor" href="#vpcmpeqd--evex-encoded-versions-">
|
||
¶
|
||
</a></h3>
|
||
<pre>(KL, VL) = (4, 128), (8, 256), (16, 512)
|
||
FOR j := 0 TO KL-1
|
||
i := j * 32
|
||
IF k2[j] OR *no writemask*
|
||
THEN
|
||
/* signed comparison */
|
||
IF (EVEX.b = 1) AND (SRC2 *is memory*)
|
||
THEN CMP := SRC1[i+31:i] = SRC2[31:0];
|
||
ELSE CMP := SRC1[i+31:i] = SRC2[i+31:i];
|
||
FI;
|
||
IF CMP = TRUE
|
||
THEN DEST[j] := 1;
|
||
ELSE DEST[j] := 0; FI;
|
||
ELSE DEST[j] := 0
|
||
; zeroing-masking only
|
||
FI;
|
||
ENDFOR
|
||
DEST[MAX_KL-1:KL] := 0
|
||
</pre>
|
||
<h2 id="intel-c-c++-compiler-intrinsic-equivalents">Intel C/C++ Compiler Intrinsic Equivalents<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalents">
|
||
¶
|
||
</a></h2>
|
||
<pre>VPCMPEQB __mmask64 _mm512_cmpeq_epi8_mask(__m512i a, __m512i b);
|
||
</pre>
|
||
<pre>VPCMPEQB __mmask64 _mm512_mask_cmpeq_epi8_mask(__mmask64 k, __m512i a, __m512i b);
|
||
</pre>
|
||
<pre>VPCMPEQB __mmask32 _mm256_cmpeq_epi8_mask(__m256i a, __m256i b);
|
||
</pre>
|
||
<pre>VPCMPEQB __mmask32 _mm256_mask_cmpeq_epi8_mask(__mmask32 k, __m256i a, __m256i b);
|
||
</pre>
|
||
<pre>VPCMPEQB __mmask16 _mm_cmpeq_epi8_mask(__m128i a, __m128i b);
|
||
</pre>
|
||
<pre>VPCMPEQB __mmask16 _mm_mask_cmpeq_epi8_mask(__mmask16 k, __m128i a, __m128i b);
|
||
</pre>
|
||
<pre>VPCMPEQW __mmask32 _mm512_cmpeq_epi16_mask(__m512i a, __m512i b);
|
||
</pre>
|
||
<pre>VPCMPEQW __mmask32 _mm512_mask_cmpeq_epi16_mask(__mmask32 k, __m512i a, __m512i b);
|
||
</pre>
|
||
<pre>VPCMPEQW __mmask16 _mm256_cmpeq_epi16_mask(__m256i a, __m256i b);
|
||
</pre>
|
||
<pre>VPCMPEQW __mmask16 _mm256_mask_cmpeq_epi16_mask(__mmask16 k, __m256i a, __m256i b);
|
||
</pre>
|
||
<pre>VPCMPEQW __mmask8 _mm_cmpeq_epi16_mask(__m128i a, __m128i b);
|
||
</pre>
|
||
<pre>VPCMPEQW __mmask8 _mm_mask_cmpeq_epi16_mask(__mmask8 k, __m128i a, __m128i b);
|
||
</pre>
|
||
<pre>VPCMPEQD __mmask16 _mm512_cmpeq_epi32_mask( __m512i a, __m512i b);
|
||
</pre>
|
||
<pre>VPCMPEQD __mmask16 _mm512_mask_cmpeq_epi32_mask(__mmask16 k, __m512i a, __m512i b);
|
||
</pre>
|
||
<pre>VPCMPEQD __mmask8 _mm256_cmpeq_epi32_mask(__m256i a, __m256i b);
|
||
</pre>
|
||
<pre>VPCMPEQD __mmask8 _mm256_mask_cmpeq_epi32_mask(__mmask8 k, __m256i a, __m256i b);
|
||
</pre>
|
||
<pre>VPCMPEQD __mmask8 _mm_cmpeq_epi32_mask(__m128i a, __m128i b);
|
||
</pre>
|
||
<pre>VPCMPEQD __mmask8 _mm_mask_cmpeq_epi32_mask(__mmask8 k, __m128i a, __m128i b);
|
||
</pre>
|
||
<pre>PCMPEQB __m64 _mm_cmpeq_pi8 (__m64 m1, __m64 m2)
|
||
</pre>
|
||
<pre>PCMPEQW __m64 _mm_cmpeq_pi16 (__m64 m1, __m64 m2)
|
||
</pre>
|
||
<pre>PCMPEQD __m64 _mm_cmpeq_pi32 (__m64 m1, __m64 m2)
|
||
</pre>
|
||
<pre>(V)PCMPEQB __m128i _mm_cmpeq_epi8 ( __m128i a, __m128i b)
|
||
</pre>
|
||
<pre>(V)PCMPEQW __m128i _mm_cmpeq_epi16 ( __m128i a, __m128i b)
|
||
</pre>
|
||
<pre>(V)PCMPEQD __m128i _mm_cmpeq_epi32 ( __m128i a, __m128i b)
|
||
</pre>
|
||
<pre>VPCMPEQB __m256i _mm256_cmpeq_epi8 ( __m256i a, __m256i b)
|
||
</pre>
|
||
<pre>VPCMPEQW __m256i _mm256_cmpeq_epi16 ( __m256i a, __m256i b)
|
||
</pre>
|
||
<pre>VPCMPEQD __m256i _mm256_cmpeq_epi32 ( __m256i a, __m256i b)
|
||
</pre>
|
||
<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
|
||
¶
|
||
</a></h2>
|
||
<p>None.</p>
|
||
<h2 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
|
||
¶
|
||
</a></h2>
|
||
<p>None.</p>
|
||
<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
|
||
¶
|
||
</a></h2>
|
||
<p>Non-EVEX-encoded instruction, see <span class="not-imported">Table 2-21</span>, “Type 4 Class Exception Conditions.”</p>
|
||
<p>EVEX-encoded VPCMPEQD, see <span class="not-imported">Table 2-49</span>, “Type E4 Class Exception Conditions.”</p>
|
||
<p>EVEX-encoded VPCMPEQB/W, see Exceptions Type E4.nb in <span class="not-imported">Table 2-49</span>, “Type E4 Class Exception Conditions.”</p><footer><p>
|
||
This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
|
||
inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
|
||
ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
|
||
</p></footer></body></html>
|