forked from NRZCode/ia32-64
163 lines
6.1 KiB
HTML
163 lines
6.1 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>NOT
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— One's Complement Negation</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>NOT
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— One's Complement Negation</h1>
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<table>
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<tr>
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<th>Opcode</th>
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<th>Instruction</th>
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<th>Op/En</th>
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<th>64-Bit Mode</th>
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<th>Compat/Leg Mode</th>
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<th>Description</th></tr>
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<tr>
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<td>F6 /2</td>
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<td>NOT r/m8</td>
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<td>M</td>
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<td>Valid</td>
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<td>Valid</td>
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<td>Reverse each bit of r/m8.</td></tr>
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<tr>
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<td>REX + F6 /2</td>
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<td>NOT r/m8<sup>1</sup></td>
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<td>M</td>
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<td>Valid</td>
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<td>N.E.</td>
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<td>Reverse each bit of r/m8.</td></tr>
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<tr>
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<td>F7 /2</td>
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<td>NOT r/m16</td>
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<td>M</td>
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<td>Valid</td>
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<td>Valid</td>
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<td>Reverse each bit of r/m16.</td></tr>
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<tr>
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<td>F7 /2</td>
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<td>NOT r/m32</td>
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<td>M</td>
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<td>Valid</td>
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<td>Valid</td>
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<td>Reverse each bit of r/m32.</td></tr>
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<tr>
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<td>REX.W + F7 /2</td>
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<td>NOT r/m64</td>
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<td>M</td>
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<td>Valid</td>
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<td>N.E.</td>
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<td>Reverse each bit of r/m64.</td></tr></table>
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<blockquote>
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<p>1. In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.</p></blockquote>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>M</td>
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<td>ModRM:r/m (r, w)</td>
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<td>N/A</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Performs a bitwise NOT operation (each 1 is set to 0, and each 0 is set to 1) on the destination operand and stores the result in the destination operand location. The destination operand can be a register or a memory location.</p>
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<p>This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.</p>
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<p>In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<pre>DEST := NOT DEST;
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</pre>
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<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="protected-mode-exceptions">Protected Mode Exceptions<a class="anchor" href="#protected-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td rowspan="3">#GP(0)</td>
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<td>If the destination operand points to a non-writable segment.</td></tr>
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<tr>
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<td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
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<tr>
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<td>If the DS, ES, FS, or GS register contains a NULL segment selector.</td></tr>
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<tr>
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<td>#SS(0)</td>
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<td>If a memory operand effective address is outside the SS segment limit.</td></tr>
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<tr>
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<td>#PF(fault-code)</td>
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<td>If a page fault occurs.</td></tr>
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<tr>
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<td>#AC(0)</td>
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<td>If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.</td></tr>
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<tr>
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<td>#UD</td>
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<td>If the LOCK prefix is used but the destination is not a memory operand.</td></tr></table>
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<h2 class="exceptions" id="real-address-mode-exceptions">Real-Address Mode Exceptions<a class="anchor" href="#real-address-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td>#GP</td>
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<td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
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<tr>
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<td>#SS</td>
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<td>If a memory operand effective address is outside the SS segment limit.</td></tr>
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<tr>
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<td>#UD</td>
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<td>If the LOCK prefix is used but the destination is not a memory operand.</td></tr></table>
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<h2 class="exceptions" id="virtual-8086-mode-exceptions">Virtual-8086 Mode Exceptions<a class="anchor" href="#virtual-8086-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td>#GP(0)</td>
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<td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
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<tr>
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<td>#SS(0)</td>
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<td>If a memory operand effective address is outside the SS segment limit.</td></tr>
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<tr>
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<td>#PF(fault-code)</td>
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<td>If a page fault occurs.</td></tr>
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<tr>
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<td>#AC(0)</td>
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<td>If alignment checking is enabled and an unaligned memory reference is made.</td></tr>
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<tr>
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<td>#UD</td>
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<td>If the LOCK prefix is used but the destination is not a memory operand.</td></tr></table>
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<h2 class="exceptions" id="compatibility-mode-exceptions">Compatibility Mode Exceptions<a class="anchor" href="#compatibility-mode-exceptions">
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¶
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</a></h2>
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<p>Same as for protected mode exceptions.</p>
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<h2 class="exceptions" id="64-bit-mode-exceptions">64-Bit Mode Exceptions<a class="anchor" href="#64-bit-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td>#SS(0)</td>
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<td>If a memory address referencing the SS segment is in a non-canonical form.</td></tr>
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<tr>
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<td>#GP(0)</td>
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<td>If the memory address is in a non-canonical form.</td></tr>
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<tr>
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<td>#PF(fault-code)</td>
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<td>If a page fault occurs.</td></tr>
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<tr>
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<td>#AC(0)</td>
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<td>If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.</td></tr>
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<tr>
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<td>#UD</td>
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<td>If the LOCK prefix is used but the destination is not a memory operand.</td></tr></table><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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