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<!DOCTYPE html>
<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>MOVSHDUP
— Replicate Single Precision Floating-Point Values</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>MOVSHDUP
— Replicate Single Precision Floating-Point Values</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op / En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>F3 0F 16 /r MOVSHDUP xmm1, xmm2/m128</td>
<td>A</td>
<td>V/V</td>
<td>SSE3</td>
<td>Move odd index single precision floating-point values from xmm2/mem and duplicate each element into xmm1.</td></tr>
<tr>
<td>VEX.128.F3.0F.WIG 16 /r VMOVSHDUP xmm1, xmm2/m128</td>
<td>A</td>
<td>V/V</td>
<td>AVX</td>
<td>Move odd index single precision floating-point values from xmm2/mem and duplicate each element into xmm1.</td></tr>
<tr>
<td>VEX.256.F3.0F.WIG 16 /r VMOVSHDUP ymm1, ymm2/m256</td>
<td>A</td>
<td>V/V</td>
<td>AVX</td>
<td>Move odd index single precision floating-point values from ymm2/mem and duplicate each element into ymm1.</td></tr>
<tr>
<td>EVEX.128.F3.0F.W0 16 /r VMOVSHDUP xmm1 {k1}{z}, xmm2/m128</td>
<td>B</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Move odd index single precision floating-point values from xmm2/m128 and duplicate each element into xmm1 under writemask.</td></tr>
<tr>
<td>EVEX.256.F3.0F.W0 16 /r VMOVSHDUP ymm1 {k1}{z}, ymm2/m256</td>
<td>B</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Move odd index single precision floating-point values from ymm2/m256 and duplicate each element into ymm1 under writemask.</td></tr>
<tr>
<td>EVEX.512.F3.0F.W0 16 /r VMOVSHDUP zmm1 {k1}{z}, zmm2/m512</td>
<td>B</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Move odd index single precision floating-point values from zmm2/m512 and duplicate each element into zmm1 under writemask.</td></tr></table>
<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
</a></h2>
<table>
<tr>
<th>Op/En</th>
<th>Tuple Type</th>
<th>Operand 1</th>
<th>Operand 2</th>
<th>Operand 3</th>
<th>Operand 4</th></tr>
<tr>
<td>A</td>
<td>N/A</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>N/A</td>
<td>N/A</td></tr>
<tr>
<td>B</td>
<td>Full Mem</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>N/A</td>
<td>N/A</td></tr></table>
<h2 id="description">Description<a class="anchor" href="#description">
</a></h2>
<p>Duplicates odd-indexed single precision floating-point values from the source operand (the second operand) to adjacent element pair in the destination operand (the first operand). See <a href='movshdup.html#fig-4-3'>Figure 4-3</a>. The source operand is an XMM, YMM or ZMM register or 128, 256 or 512-bit memory location and the destination operand is an XMM, YMM or ZMM register.</p>
<p>128-bit Legacy SSE version: Bits (MAXVL-1:128) of the corresponding destination register remain unchanged.</p>
<p>VEX.128 encoded version: Bits (MAXVL-1:128) of the destination register are zeroed.</p>
<p>VEX.256 encoded version: Bits (MAXVL-1:256) of the destination register are zeroed.</p>
<p>EVEX encoded version: The destination operand is updated at 32-bit granularity according to the writemask.</p>
<p>Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.</p>
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<figcaption><a href='movshdup.html#fig-4-3'>Figure 4-3</a>. MOVSHDUP Operation</figcaption></figure>
<h2 id="operation">Operation<a class="anchor" href="#operation">
</a></h2>
<h3 id="vmovshdup--evex-encoded-versions-">VMOVSHDUP (EVEX Encoded Versions)<a class="anchor" href="#vmovshdup--evex-encoded-versions-">
</a></h3>
<pre>(KL, VL) = (4, 128), (8, 256), (16, 512)
TMP_SRC[31:0] := SRC[63:32]
TMP_SRC[63:32] := SRC[63:32]
TMP_SRC[95:64] := SRC[127:96]
TMP_SRC[127:96] := SRC[127:96]
IF VL &gt;= 256
TMP_SRC[159:128] := SRC[191:160]
TMP_SRC[191:160] := SRC[191:160]
TMP_SRC[223:192] := SRC[255:224]
TMP_SRC[255:224] := SRC[255:224]
FI;
IF VL &gt;= 512
TMP_SRC[287:256] := SRC[319:288]
TMP_SRC[319:288] := SRC[319:288]
TMP_SRC[351:320] := SRC[383:352]
TMP_SRC[383:352] := SRC[383:352]
TMP_SRC[415:384] := SRC[447:416]
TMP_SRC[447:416] := SRC[447:416]
TMP_SRC[479:448] := SRC[511:480]
TMP_SRC[511:480] := SRC[511:480]
FI;
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] := TMP_SRC[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
</pre>
<h3 id="vmovshdup--vex-256-encoded-version-">VMOVSHDUP (VEX.256 Encoded Version)<a class="anchor" href="#vmovshdup--vex-256-encoded-version-">
</a></h3>
<pre>DEST[31:0] := SRC[63:32]
DEST[63:32] := SRC[63:32]
DEST[95:64] := SRC[127:96]
DEST[127:96] := SRC[127:96]
DEST[159:128] := SRC[191:160]
DEST[191:160] := SRC[191:160]
DEST[223:192] := SRC[255:224]
DEST[255:224] := SRC[255:224]
DEST[MAXVL-1:256] := 0
</pre>
<h3 id="vmovshdup--vex-128-encoded-version-">VMOVSHDUP (VEX.128 Encoded Version)<a class="anchor" href="#vmovshdup--vex-128-encoded-version-">
</a></h3>
<pre>DEST[31:0] := SRC[63:32]
DEST[63:32] := SRC[63:32]
DEST[95:64] := SRC[127:96]
DEST[127:96] := SRC[127:96]
DEST[MAXVL-1:128] := 0
</pre>
<h3 id="movshdup--128-bit-legacy-sse-version-">MOVSHDUP (128-bit Legacy SSE Version)<a class="anchor" href="#movshdup--128-bit-legacy-sse-version-">
</a></h3>
<pre>DEST[31:0] := SRC[63:32]
DEST[63:32] := SRC[63:32]
DEST[95:64] := SRC[127:96]
DEST[127:96] := SRC[127:96]
DEST[MAXVL-1:128] (Unmodified)
</pre>
<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
</a></h2>
<pre>VMOVSHDUP __m512 _mm512_movehdup_ps( __m512 a);
</pre>
<pre>VMOVSHDUP __m512 _mm512_mask_movehdup_ps(__m512 s, __mmask16 k, __m512 a);
</pre>
<pre>VMOVSHDUP __m512 _mm512_maskz_movehdup_ps( __mmask16 k, __m512 a);
</pre>
<pre>VMOVSHDUP __m256 _mm256_mask_movehdup_ps(__m256 s, __mmask8 k, __m256 a);
</pre>
<pre>VMOVSHDUP __m256 _mm256_maskz_movehdup_ps( __mmask8 k, __m256 a);
</pre>
<pre>VMOVSHDUP __m128 _mm_mask_movehdup_ps(__m128 s, __mmask8 k, __m128 a);
</pre>
<pre>VMOVSHDUP __m128 _mm_maskz_movehdup_ps( __mmask8 k, __m128 a);
</pre>
<pre>VMOVSHDUP __m256 _mm256_movehdup_ps (__m256 a);
</pre>
<pre>VMOVSHDUP __m128 _mm_movehdup_ps (__m128 a);
</pre>
<h2 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
</a></h2>
<p>None.</p>
<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
</a></h2>
<p>Non-EVEX-encoded instruction, see <span class="not-imported">Table 2-21</span>, “Type 4 Class Exception Conditions.”</p>
<p>EVEX-encoded instruction, see Exceptions Type E4NF.nb in <span class="not-imported">Table 2-50</span>, “Type E4NF Class Exception Conditions.”</p>
<p>Additionally:</p>
<table>
<tr>
<td>#UD</td>
<td>If EVEX.vvvv != 1111B or VEX.vvvv != 1111B.</td></tr></table><footer><p>
This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
</p></footer></body></html>
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