forked from NRZCode/ia32-64
119 lines
4.9 KiB
HTML
119 lines
4.9 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>MOVMSKPS
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— Extract Packed Single Precision Floating-Point Sign Mask</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>MOVMSKPS
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— Extract Packed Single Precision Floating-Point Sign Mask</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32-bit Mode</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>NP 0F 50 /r MOVMSKPS reg, xmm</td>
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<td>RM</td>
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<td>V/V</td>
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<td>SSE</td>
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<td>Extract 4-bit sign mask from xmm and store in reg. The upper bits of r32 or r64 are filled with zeros.</td></tr>
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<tr>
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<td>VEX.128.0F.WIG 50 /r VMOVMSKPS reg, xmm2</td>
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<td>RM</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Extract 4-bit sign mask from xmm2 and store in reg. The upper bits of r32 or r64 are zeroed.</td></tr>
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<tr>
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<td>VEX.256.0F.WIG 50 /r VMOVMSKPS reg, ymm2</td>
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<td>RM</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Extract 8-bit sign mask from ymm2 and store in reg. The upper bits of r32 or r64 are zeroed.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<sup>1</sup><a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<blockquote>
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<p>1. ModRM.MOD = 011B required</p></blockquote>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>RM</td>
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<td>ModRM:reg (w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Extracts the sign bits from the packed single precision floating-point values in the source operand (second operand), formats them into a 4- or 8-bit mask, and stores the mask in the destination operand (first operand). The source operand is an XMM or YMM register, and the destination operand is a general-purpose register. The mask is stored in the 4 or 8 low-order bits of the destination operand. The upper bits of the destination operand beyond the mask are filled with zeros.</p>
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<p>In 64-bit mode, the instruction can access additional registers (XMM8-XMM15, R8-R15) when used with a REX.R prefix. The default operand size is 64-bit in 64-bit mode.</p>
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<p>128-bit versions: The source operand is a YMM register. The destination operand is a general purpose register.</p>
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<p>VEX.256 encoded version: The source operand is a YMM register. The destination operand is a general purpose register.</p>
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<p>Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<pre>DEST[0] := SRC[31];
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DEST[1] := SRC[63];
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DEST[2] := SRC[95];
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DEST[3] := SRC[127];
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IF DEST = r32
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THEN DEST[31:4] := ZeroExtend;
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ELSE DEST[63:4] := ZeroExtend;
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FI;
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</pre>
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<h3 id="-v-movmskps--128-bit-version-">(V)MOVMSKPS (128-bit version)<a class="anchor" href="#-v-movmskps--128-bit-version-">
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¶
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</a></h3>
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<pre>DEST[0] := SRC[31]
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DEST[1] := SRC[63]
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DEST[2] := SRC[95]
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DEST[3] := SRC[127]
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IF DEST = r32
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THEN DEST[31:4] := 0;
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ELSE DEST[63:4] := 0;
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FI
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</pre>
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<h3 id="vmovmskps--vex-256-encoded-version-">VMOVMSKPS (VEX.256 encoded version)<a class="anchor" href="#vmovmskps--vex-256-encoded-version-">
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¶
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</a></h3>
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<pre>DEST[0] := SRC[31]
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DEST[1] := SRC[63]
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DEST[2] := SRC[95]
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DEST[3] := SRC[127]
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DEST[4] := SRC[159]
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DEST[5] := SRC[191]
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DEST[6] := SRC[223]
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DEST[7] := SRC[255]
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IF DEST = r32
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THEN DEST[31:8] := 0;
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ELSE DEST[63:8] := 0;
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FI
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</pre>
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<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h2>
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<pre>int _mm_movemask_ps(__m128 a)
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</pre>
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<pre>int _mm256_movemask_ps(__m256 a)
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</pre>
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<h2 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h2>
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<p>See <span class="not-imported">Table 2-24</span>, “Type 7 Class Exception Conditions,” additionally:</p>
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<table>
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<tr>
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<td>#UD</td>
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<td>If VEX.vvvv ≠ 1111B.</td></tr></table><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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