forked from NRZCode/ia32-64
152 lines
6.2 KiB
HTML
152 lines
6.2 KiB
HTML
<!DOCTYPE html>
|
||
<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>MOVHPS
|
||
— Move High Packed Single Precision Floating-Point Values</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>MOVHPS
|
||
— Move High Packed Single Precision Floating-Point Values</h1>
|
||
|
||
<table>
|
||
<tr>
|
||
<th>Opcode/Instruction</th>
|
||
<th>Op / En</th>
|
||
<th>64/32 bit Mode Support</th>
|
||
<th>CPUID Feature Flag</th>
|
||
<th>Description</th></tr>
|
||
<tr>
|
||
<td>NP 0F 16 /r MOVHPS xmm1, m64</td>
|
||
<td>A</td>
|
||
<td>V/V</td>
|
||
<td>SSE</td>
|
||
<td>Move two packed single precision floating-point values from m64 to high quadword of xmm1.</td></tr>
|
||
<tr>
|
||
<td>VEX.128.0F.WIG 16 /r VMOVHPS xmm2, xmm1, m64</td>
|
||
<td>B</td>
|
||
<td>V/V</td>
|
||
<td>AVX</td>
|
||
<td>Merge two packed single precision floating-point values from m64 and the low quadword of xmm1.</td></tr>
|
||
<tr>
|
||
<td>EVEX.128.0F.W0 16 /r VMOVHPS xmm2, xmm1, m64</td>
|
||
<td>D</td>
|
||
<td>V/V</td>
|
||
<td>AVX512F</td>
|
||
<td>Merge two packed single precision floating-point values from m64 and the low quadword of xmm1.</td></tr>
|
||
<tr>
|
||
<td>NP 0F 17 /r MOVHPS m64, xmm1</td>
|
||
<td>C</td>
|
||
<td>V/V</td>
|
||
<td>SSE</td>
|
||
<td>Move two packed single precision floating-point values from high quadword of xmm1 to m64.</td></tr>
|
||
<tr>
|
||
<td>VEX.128.0F.WIG 17 /r VMOVHPS m64, xmm1</td>
|
||
<td>C</td>
|
||
<td>V/V</td>
|
||
<td>AVX</td>
|
||
<td>Move two packed single precision floating-point values from high quadword of xmm1 to m64.</td></tr>
|
||
<tr>
|
||
<td>EVEX.128.0F.W0 17 /r VMOVHPS m64, xmm1</td>
|
||
<td>E</td>
|
||
<td>V/V</td>
|
||
<td>AVX512F</td>
|
||
<td>Move two packed single precision floating-point values from high quadword of xmm1 to m64.</td></tr></table>
|
||
<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
|
||
¶
|
||
</a></h2>
|
||
<table>
|
||
<tr>
|
||
<th>Op/En</th>
|
||
<th>Tuple Type</th>
|
||
<th>Operand 1</th>
|
||
<th>Operand 2</th>
|
||
<th>Operand 3</th>
|
||
<th>Operand 4</th></tr>
|
||
<tr>
|
||
<td>A</td>
|
||
<td>N/A</td>
|
||
<td>ModRM:reg (r, w)</td>
|
||
<td>ModRM:r/m (r)</td>
|
||
<td>N/A</td>
|
||
<td>N/A</td></tr>
|
||
<tr>
|
||
<td>B</td>
|
||
<td>N/A</td>
|
||
<td>ModRM:reg (w)</td>
|
||
<td>VEX.vvvv (r)</td>
|
||
<td>ModRM:r/m (r)</td>
|
||
<td>N/A</td></tr>
|
||
<tr>
|
||
<td>C</td>
|
||
<td>N/A</td>
|
||
<td>ModRM:r/m (w)</td>
|
||
<td>ModRM:reg (r)</td>
|
||
<td>N/A</td>
|
||
<td>N/A</td></tr>
|
||
<tr>
|
||
<td>D</td>
|
||
<td>Tuple2</td>
|
||
<td>ModRM:reg (w)</td>
|
||
<td>EVEX.vvvv (r)</td>
|
||
<td>ModRM:r/m (r)</td>
|
||
<td>N/A</td></tr>
|
||
<tr>
|
||
<td>E</td>
|
||
<td>Tuple2</td>
|
||
<td>ModRM:r/m (w)</td>
|
||
<td>ModRM:reg (r)</td>
|
||
<td>N/A</td>
|
||
<td>N/A</td></tr></table>
|
||
<h2 id="description">Description<a class="anchor" href="#description">
|
||
¶
|
||
</a></h2>
|
||
<p>This instruction cannot be used for register to register or memory to memory moves.</p>
|
||
<p>128-bit Legacy SSE load:</p>
|
||
<p>Moves two packed single precision floating-point values from the source 64-bit memory operand and stores them in the high 64-bits of the destination XMM register. The lower 64bits of the XMM register are preserved. Bits (MAXVL-1:128) of the corresponding destination register are preserved.</p>
|
||
<p>VEX.128 & EVEX encoded load:</p>
|
||
<p>Loads two single precision floating-point values from the source 64-bit memory operand (the third operand) and stores it in the upper 64-bits of the destination XMM register (first operand). The low 64-bits from the first source operand (the second operand) are copied to the lower 64-bits of the destination. Bits (MAXVL-1:128) of the corresponding destination register are zeroed.</p>
|
||
<p>128-bit store:</p>
|
||
<p>Stores two packed single precision floating-point values from the high 64-bits of the XMM register source (second operand) to the 64-bit memory location (first operand).</p>
|
||
<p>Note: VMOVHPS (store) (VEX.128.0F 17 /r) is legal and has the same behavior as the existing 0F 17 store. For VMOVHPS (store) VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instruction will #UD.</p>
|
||
<p>If VMOVHPS is encoded with VEX.L or EVEX.L’L= 1, an attempt to execute the instruction encoded with VEX.L or EVEX.L’L= 1 will cause an #UD exception.</p>
|
||
<h2 id="operation">Operation<a class="anchor" href="#operation">
|
||
¶
|
||
</a></h2>
|
||
<h3 id="movhps--128-bit-legacy-sse-load-">MOVHPS (128-bit Legacy SSE Load)<a class="anchor" href="#movhps--128-bit-legacy-sse-load-">
|
||
¶
|
||
</a></h3>
|
||
<pre>DEST[63:0] (Unmodified)
|
||
DEST[127:64] := SRC[63:0]
|
||
DEST[MAXVL-1:128] (Unmodified)
|
||
</pre>
|
||
<h3 id="vmovhps--vex-128-and-evex-encoded-load-">VMOVHPS (VEX.128 and EVEX Encoded Load)<a class="anchor" href="#vmovhps--vex-128-and-evex-encoded-load-">
|
||
¶
|
||
</a></h3>
|
||
<pre>DEST[63:0] := SRC1[63:0]
|
||
DEST[127:64] := SRC2[63:0]
|
||
DEST[MAXVL-1:128] := 0
|
||
</pre>
|
||
<h3 id="vmovhps--store-">VMOVHPS (Store)<a class="anchor" href="#vmovhps--store-">
|
||
¶
|
||
</a></h3>
|
||
<pre>DEST[63:0] := SRC[127:64]
|
||
</pre>
|
||
<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
|
||
¶
|
||
</a></h2>
|
||
<pre>MOVHPS __m128 _mm_loadh_pi ( __m128 a, __m64 *p)
|
||
</pre>
|
||
<pre>MOVHPS void _mm_storeh_pi (__m64 *p, __m128 a)
|
||
</pre>
|
||
<h2 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
|
||
¶
|
||
</a></h2>
|
||
<p>None.</p>
|
||
<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
|
||
¶
|
||
</a></h2>
|
||
<p>Non-EVEX-encoded instruction, see <span class="not-imported">Table 2-22</span>, “Type 5 Class Exception Conditions,” additionally:</p>
|
||
<table>
|
||
<tr>
|
||
<td>#UD</td>
|
||
<td>If VEX.L = 1.</td></tr></table>
|
||
<p>EVEX-encoded instruction, see <span class="not-imported">Table 2-57</span>, “Type E9NF Class Exception Conditions.”</p><footer><p>
|
||
This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
|
||
inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
|
||
ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
|
||
</p></footer></body></html>
|