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204 lines
7.5 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>MOVBE
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— Move Data After Swapping Bytes</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>MOVBE
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— Move Data After Swapping Bytes</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>0F 38 F0 /r MOVBE r16, m16</td>
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<td>RM</td>
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<td>V/V</td>
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<td>MOVBE</td>
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<td>Reverse byte order in m16 and move to r16.</td></tr>
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<tr>
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<td>0F 38 F0 /r MOVBE r32, m32</td>
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<td>RM</td>
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<td>V/V</td>
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<td>MOVBE</td>
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<td>Reverse byte order in m32 and move to r32.</td></tr>
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<tr>
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<td>REX.W + 0F 38 F0 /r MOVBE r64, m64</td>
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<td>RM</td>
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<td>V/N.E.</td>
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<td>MOVBE</td>
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<td>Reverse byte order in m64 and move to r64.</td></tr>
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<tr>
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<td>0F 38 F1 /r MOVBE m16, r16</td>
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<td>MR</td>
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<td>V/V</td>
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<td>MOVBE</td>
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<td>Reverse byte order in r16 and move to m16.</td></tr>
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<tr>
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<td>0F 38 F1 /r MOVBE m32, r32</td>
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<td>MR</td>
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<td>V/V</td>
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<td>MOVBE</td>
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<td>Reverse byte order in r32 and move to m32.</td></tr>
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<tr>
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<td>REX.W + 0F 38 F1 /r MOVBE m64, r64</td>
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<td>MR</td>
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<td>V/N.E.</td>
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<td>MOVBE</td>
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<td>Reverse byte order in r64 and move to m64.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>RM</td>
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<td>ModRM:reg (w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr>
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<tr>
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<td>MR</td>
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<td>ModRM:r/m (w)</td>
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<td>ModRM:reg (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Performs a byte swap operation on the data copied from the second operand (source operand) and store the result in the first operand (destination operand). The source operand can be a general-purpose register, or memory location; the destination register can be a general-purpose register, or a memory location; however, both operands can not be registers, and only one operand can be a memory location. Both operands must be the same size, which can be a word, a doubleword or quadword.</p>
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<p>The MOVBE instruction is provided for swapping the bytes on a read from memory or on a write to memory; thus providing support for converting little-endian values to big-endian format and vice versa.</p>
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<p>In 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<pre>TEMP := SRC
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IF ( OperandSize = 16)
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THEN
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DEST[7:0] := TEMP[15:8];
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DEST[15:8] := TEMP[7:0];
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ELES IF ( OperandSize = 32)
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DEST[7:0] := TEMP[31:24];
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DEST[15:8] := TEMP[23:16];
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DEST[23:16] := TEMP[15:8];
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DEST[31:23] := TEMP[7:0];
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ELSE IF ( OperandSize = 64)
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DEST[7:0] := TEMP[63:56];
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DEST[15:8] := TEMP[55:48];
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DEST[23:16] := TEMP[47:40];
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DEST[31:24] := TEMP[39:32];
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DEST[39:32] := TEMP[31:24];
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DEST[47:40] := TEMP[23:16];
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DEST[55:48] := TEMP[15:8];
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DEST[63:56] := TEMP[7:0];
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FI;
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</pre>
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<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="protected-mode-exceptions">Protected Mode Exceptions<a class="anchor" href="#protected-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td rowspan="3">#GP(0)</td>
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<td>If the destination operand is in a non-writable segment.</td></tr>
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<tr>
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<td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
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<tr>
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<td>If the DS, ES, FS, or GS register contains a NULL segment selector.</td></tr>
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<tr>
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<td>#SS(0)</td>
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<td>If a memory operand effective address is outside the SS segment limit.</td></tr>
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<tr>
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<td>#PF(fault-code)</td>
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<td>If a page fault occurs.</td></tr>
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<tr>
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<td>#AC(0)</td>
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<td>If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.</td></tr>
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<tr>
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<td rowspan="3">#UD</td>
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<td>If CPUID.01H:ECX.MOVBE[bit 22] = 0.</td></tr>
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<tr>
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<td>If the LOCK prefix is used.</td></tr>
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<tr>
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<td>If REP (F3H) prefix is used.</td></tr></table>
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<h2 class="exceptions" id="real-address-mode-exceptions">Real-Address Mode Exceptions<a class="anchor" href="#real-address-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td>#GP</td>
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<td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
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<tr>
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<td>#SS</td>
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<td>If a memory operand effective address is outside the SS segment limit.</td></tr>
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<tr>
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<td rowspan="3">#UD</td>
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<td>If CPUID.01H:ECX.MOVBE[bit 22] = 0.</td></tr>
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<tr>
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<td>If the LOCK prefix is used.</td></tr>
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<tr>
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<td>If REP (F3H) prefix is used.</td></tr></table>
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<h2 class="exceptions" id="virtual-8086-mode-exceptions">Virtual-8086 Mode Exceptions<a class="anchor" href="#virtual-8086-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td>#GP(0)</td>
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<td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
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<tr>
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<td>#SS(0)</td>
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<td>If a memory operand effective address is outside the SS segment limit.</td></tr>
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<tr>
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<td>#PF(fault-code)</td>
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<td>If a page fault occurs.</td></tr>
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<tr>
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<td>#AC(0)</td>
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<td>If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.</td></tr>
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<tr>
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<td rowspan="4">#UD</td>
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<td>If CPUID.01H:ECX.MOVBE[bit 22] = 0.</td></tr>
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<tr>
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<td>If the LOCK prefix is used.</td></tr>
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<tr>
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<td>If REP (F3H) prefix is used.</td></tr>
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<tr>
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<td>If REPNE (F2H) prefix is used and CPUID.01H:ECX.SSE4_2[bit 20] = 0.</td></tr></table>
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<h2 class="exceptions" id="compatibility-mode-exceptions">Compatibility Mode Exceptions<a class="anchor" href="#compatibility-mode-exceptions">
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¶
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</a></h2>
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<p>Same exceptions as in protected mode.</p>
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<h2 class="exceptions" id="64-bit-mode-exceptions">64-Bit Mode Exceptions<a class="anchor" href="#64-bit-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td>#GP(0)</td>
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<td>If the memory address is in a non-canonical form.</td></tr>
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<tr>
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<td>#SS(0)</td>
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<td>If the stack address is in a non-canonical form.</td></tr>
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<tr>
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<td>#PF(fault-code)</td>
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<td>If a page fault occurs.</td></tr>
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<tr>
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<td>#AC(0)</td>
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<td>If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.</td></tr>
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<tr>
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<td rowspan="3">#UD</td>
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<td>If CPUID.01H:ECX.MOVBE[bit 22] = 0.</td></tr>
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<tr>
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<td>If the LOCK prefix is used.</td></tr>
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<tr>
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<td>If REP (F3H) prefix is used.</td></tr></table><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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