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182 lines
6.6 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>LDTILECFG
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— Load Tile Configuration</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>LDTILECFG
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— Load Tile Configuration</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>VEX.128.NP.0F38.W0 49 !(11):000:bbb LDTILECFG m512</td>
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<td>A</td>
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<td>V/N.E.</td>
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<td>AMX-TILE</td>
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<td>Load tile configuration as specified in m512.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>N/A</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h3 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h3>
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<p>The LDTILECFG instruction takes an operand containing a pointer to a 64-byte memory location containing the description of the tiles to be supported. In order to configure the tiles, the AMX-TILE bit in CPUID must be set and the operating system has to have enabled the tiles architecture.</p>
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<p>The memory area contains the palette and describes how many tiles are being used and defines each tile in terms of rows and column bytes. Requests must be compatible with the restrictions provided by CPUID; see <a href='cpuid.html#tbl-3-10'>Table 3-10</a> below.</p>
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<figure id="tbl-3-10">
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<table>
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<tr>
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<th>Byte(s)</th>
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<th>Field Name</th>
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<th>Description</th></tr>
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<tr>
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<td>0</td>
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<td>palette</td>
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<td>Palette selects the supported configuration of the tiles that will be used.</td></tr>
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<tr>
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<td>1</td>
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<td>start_row</td>
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<td>start_row is used for storing the restart values for interrupted operations.</td></tr>
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<tr>
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<td>2-15</td>
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<td>reserved, must be zero</td>
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<td></td></tr>
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<tr>
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<td>16-17</td>
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<td>tile0.colsb</td>
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<td>Tile 0 bytes per row.</td></tr>
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<tr>
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<td>18-19</td>
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<td>tile1.colsb</td>
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<td>Tile 1 bytes per row.</td></tr>
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<tr>
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<td>20-21</td>
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<td>tile2.colsb</td>
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<td>Tile 2 bytes per row.</td></tr>
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<tr>
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<td>...</td>
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<td>(sequence continues)</td>
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<td></td></tr>
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<tr>
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<td>30-31</td>
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<td>tile7.colsb</td>
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<td>Tile 7 bytes per row.</td></tr>
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<tr>
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<td>32-47</td>
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<td>reserved, must be zero</td>
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<td></td></tr>
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<tr>
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<td>48</td>
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<td>tile0.rows</td>
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<td>Tile 0 rows.</td></tr>
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<tr>
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<td>49</td>
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<td>tile1.rows</td>
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<td>Tile 1 rows.</td></tr>
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<tr>
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<td>50</td>
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<td>tile2.rows</td>
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<td>Tile 2 rows.</td></tr>
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<tr>
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<td>...</td>
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<td>(sequence continues)</td>
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<td></td></tr>
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<tr>
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<td>55</td>
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<td>tile7.rows</td>
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<td>Tile 7 rows.</td></tr>
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<tr>
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<td>56-63</td>
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<td>reserved, must be zero</td>
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<td></td></tr></table>
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<figcaption><a href='cpuid.html#tbl-3-10'>Table 3-10</a>. Memory Area Layout</figcaption></figure>
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<p>If a tile row and column pair is not used to specify tile parameters, they must have the value zero. All enabled tiles (based on the palette) must be configured. Specifying tile parameters for more tiles than the implementation limit or the palette limit results in a #GP fault.</p>
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<p>If the palette_id is zero, that signifies the INIT state for both TILECFG and TILEDATA. Tiles are zeroed in the INIT state. The only legal non-INIT value for palette_id is 1.</p>
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<p>Any attempt to execute the LDTILECFG instruction inside an Intel TSX transaction will result in a transaction abort.</p>
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<h3 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h3>
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<h4 id="ldtilecfg-mem">LDTILECFG mem<a class="anchor" href="#ldtilecfg-mem">
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¶
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</a></h4>
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<pre>error := False
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buf := read_memory(mem, 64)
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temp_tilecfg.palette_id := buf.byte[0]
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if temp_tilecfg.palette_id > max_palette:
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error := True
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if not xcr0_supports_palette(temp_tilecfg.palette_id):
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error := True
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if temp_tilecfg.palette_id !=0:
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temp_tilecfg.start_row := buf.byte[1]
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if buf.byte[2..15] is nonzero:
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error := True
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p := 16
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# configure columns
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for n in 0 ... palette_table[temp_tilecfg.palette_id].max_names-1:
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temp_tilecfg.t[n].colsb:= buf.word[p/2]
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p := p + 2
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if temp_tilecfg.t[n].colsb > palette_table[temp_tilecfg.palette_id].bytes_per_row:
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error := True
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if nonzero(buf[p...47]):
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error := True
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# configure rows
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p := 48
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for n in 0 ... palette_table[temp_tilecfg.palette_id].max_names-1:
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temp_tilecfg.t[n].rows:= buf.byte[p]
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if temp_tilecfg.t[n].rows > palette_table[temp_tilecfg.palette_id].max_rows:
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error := True
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p := p + 1
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if nonzero(buf[p...63]):
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error := True
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# validate each tile's row & col configs are reasonable and enable the valid tiles
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for n in 0 ... palette_table[temp_tilecfg.palette_id].max_names-1:
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if temp_tilecfg.t[n].rows !=0 and temp_tilecfg.t[n].colsb != 0:
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temp_tilecfg.t[n].valid := 1
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elif temp_tilecfg.t[n].rows == 0 and temp_tilecfg.t[n].colsb == 0:
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temp_tilecfg.t[n].valid := 0
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else:
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error := True// one of rows or colsbwas 0 but not both.
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if error:
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#GP
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elif temp_tilecfg.palette_id == 0:
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TILES_CONFIGURED := 0// init state
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tilecfg := 0// equivalent to 64B of zeros
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zero_all_tile_data()
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else:
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tilecfg := temp_tilecfg
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zero_all_tile_data()
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TILES_CONFIGURED := 1
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</pre>
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<h3 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h3>
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<pre>LDTILECFG void _tile_loadconfig(const void *);
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</pre>
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<h3 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
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¶
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</a></h3>
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<p>None.</p>
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<h3 class="exceptions" id="exceptions">Exceptions<a class="anchor" href="#exceptions">
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¶
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</a></h3>
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<p>AMX-E1; see Section 2.10, “Intel® AMX Instruction Exception Classes,” for details.</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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