forked from NRZCode/ia32-64
105 lines
3.8 KiB
HTML
105 lines
3.8 KiB
HTML
<!DOCTYPE html>
|
||
<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>KANDW/KANDB/KANDQ/KANDD
|
||
— Bitwise Logical AND Masks</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>KANDW/KANDB/KANDQ/KANDD
|
||
— Bitwise Logical AND Masks</h1>
|
||
|
||
|
||
|
||
|
||
<table>
|
||
<tr>
|
||
<th>Opcode/Instruction</th>
|
||
<th>Op/En</th>
|
||
<th>64/32 bit Mode Support</th>
|
||
<th>CPUID Feature Flag</th>
|
||
<th>Description</th></tr>
|
||
<tr>
|
||
<td>VEX.L1.0F.W0 41 /r KANDW k1, k2, k3</td>
|
||
<td>RVR</td>
|
||
<td>V/V</td>
|
||
<td>AVX512F</td>
|
||
<td>Bitwise AND 16 bits masks k2 and k3 and place result in k1.</td></tr>
|
||
<tr>
|
||
<td>VEX.L1.66.0F.W0 41 /r KANDB k1, k2, k3</td>
|
||
<td>RVR</td>
|
||
<td>V/V</td>
|
||
<td>AVX512DQ</td>
|
||
<td>Bitwise AND 8 bits masks k2 and k3 and place result in k1.</td></tr>
|
||
<tr>
|
||
<td>VEX.L1.0F.W1 41 /r KANDQ k1, k2, k3</td>
|
||
<td>RVR</td>
|
||
<td>V/V</td>
|
||
<td>AVX512BW</td>
|
||
<td>Bitwise AND 64 bits masks k2 and k3 and place result in k1.</td></tr>
|
||
<tr>
|
||
<td>VEX.L1.66.0F.W1 41 /r KANDD k1, k2, k3</td>
|
||
<td>RVR</td>
|
||
<td>V/V</td>
|
||
<td>AVX512BW</td>
|
||
<td>Bitwise AND 32 bits masks k2 and k3 and place result in k1.</td></tr></table>
|
||
<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
|
||
¶
|
||
</a></h2>
|
||
<table>
|
||
<tr>
|
||
<th>Op/En</th>
|
||
<th>Operand 1</th>
|
||
<th>Operand 2</th>
|
||
<th>Operand 3</th></tr>
|
||
<tr>
|
||
<td>RVR</td>
|
||
<td>ModRM:reg (w)</td>
|
||
<td>VEX.1vvv (r)</td>
|
||
<td>ModRM:r/m (r, ModRM:[7:6] must be 11b)</td></tr></table>
|
||
<h2 id="description">Description<a class="anchor" href="#description">
|
||
¶
|
||
</a></h2>
|
||
<p>Performs a bitwise AND between the vector mask k2 and the vector mask k3, and writes the result into vector mask k1.</p>
|
||
<h2 id="operation">Operation<a class="anchor" href="#operation">
|
||
¶
|
||
</a></h2>
|
||
<h3 id="kandw">KANDW<a class="anchor" href="#kandw">
|
||
¶
|
||
</a></h3>
|
||
<pre>DEST[15:0] := SRC1[15:0] BITWISE AND SRC2[15:0]
|
||
DEST[MAX_KL-1:16] := 0
|
||
</pre>
|
||
<h3 id="kandb">KANDB<a class="anchor" href="#kandb">
|
||
¶
|
||
</a></h3>
|
||
<pre>DEST[7:0] := SRC1[7:0] BITWISE AND SRC2[7:0]
|
||
DEST[MAX_KL-1:8] := 0
|
||
</pre>
|
||
<h3 id="kandq">KANDQ<a class="anchor" href="#kandq">
|
||
¶
|
||
</a></h3>
|
||
<pre>DEST[63:0] := SRC1[63:0] BITWISE AND SRC2[63:0]
|
||
DEST[MAX_KL-1:64] := 0
|
||
</pre>
|
||
<h3 id="kandd">KANDD<a class="anchor" href="#kandd">
|
||
¶
|
||
</a></h3>
|
||
<pre>DEST[31:0] := SRC1[31:0] BITWISE AND SRC2[31:0]
|
||
DEST[MAX_KL-1:32] := 0
|
||
</pre>
|
||
<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
|
||
¶
|
||
</a></h2>
|
||
<pre>KANDW __mmask16 _mm512_kand(__mmask16 a, __mmask16 b);
|
||
</pre>
|
||
<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
|
||
¶
|
||
</a></h2>
|
||
<p>None.</p>
|
||
<h2 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
|
||
¶
|
||
</a></h2>
|
||
<p>None.</p>
|
||
<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
|
||
¶
|
||
</a></h2>
|
||
<p>See <span class="not-imported">Table 2-63</span>, “TYPE K20 Exception Definition (VEX-Encoded OpMask Instructions w/o Memory Arg).”</p><footer><p>
|
||
This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
|
||
inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
|
||
ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
|
||
</p></footer></body></html>
|