forked from NRZCode/ia32-64
162 lines
6.6 KiB
HTML
162 lines
6.6 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>GF2P8MULB
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— Galois Field Multiply Bytes</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>GF2P8MULB
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— Galois Field Multiply Bytes</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>66 0F38 CF /r GF2P8MULB xmm1, xmm2/m128</td>
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<td>A</td>
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<td>V/V</td>
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<td>GFNI</td>
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<td>Multiplies elements in the finite field GF(2^8).</td></tr>
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<tr>
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<td>VEX.128.66.0F38.W0 CF /r VGF2P8MULB xmm1, xmm2, xmm3/m128</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX GFNI</td>
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<td>Multiplies elements in the finite field GF(2^8).</td></tr>
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<tr>
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<td>VEX.256.66.0F38.W0 CF /r VGF2P8MULB ymm1, ymm2, ymm3/m256</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX GFNI</td>
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<td>Multiplies elements in the finite field GF(2^8).</td></tr>
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<tr>
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<td>EVEX.128.66.0F38.W0 CF /r VGF2P8MULB xmm1{k1}{z}, xmm2, xmm3/m128</td>
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<td>C</td>
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<td>V/V</td>
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<td>AVX512VL GFNI</td>
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<td>Multiplies elements in the finite field GF(2^8).</td></tr>
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<tr>
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<td>EVEX.256.66.0F38.W0 CF /r VGF2P8MULB ymm1{k1}{z}, ymm2, ymm3/m256</td>
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<td>C</td>
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<td>V/V</td>
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<td>AVX512VL GFNI</td>
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<td>Multiplies elements in the finite field GF(2^8).</td></tr>
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<tr>
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<td>EVEX.512.66.0F38.W0 CF /r VGF2P8MULB zmm1{k1}{z}, zmm2, zmm3/m512</td>
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<td>C</td>
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<td>V/V</td>
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<td>AVX512F GFNI</td>
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<td>Multiplies elements in the finite field GF(2^8).</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>N/A</td>
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<td>ModRM:reg (r, w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr>
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<tr>
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<td>B</td>
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<td>N/A</td>
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<td>ModRM:reg (w)</td>
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<td>VEX.vvvv (r)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td></tr>
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<tr>
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<td>C</td>
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<td>Full Mem</td>
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<td>ModRM:reg (w)</td>
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<td>EVEX.vvvv (r)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td></tr></table>
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<h3 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h3>
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<p>The instruction multiplies elements in the finite field GF(2<sup>8</sup>), operating on a byte (field element) in the first source operand and the corresponding byte in a second source operand. The field GF(2<sup>8</sup>) is represented in polynomial representation with the reduction polynomial x<sup>8</sup> + x<sup>4</sup> + x<sup>3</sup> + x + 1.</p>
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<p>This instruction does not support broadcasting.</p>
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<p>The EVEX encoded form of this instruction supports memory fault suppression. The SSE encoded forms of the instruction require16B alignment on their memory operations.</p>
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<h3 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h3>
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<pre>define gf2p8mul_byte(src1byte, src2byte):
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tword := 0
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FOR i := 0 to 7:
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IF src2byte.bit[i]:
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tword := tword XOR (src1byte<< i)
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* carry out polynomial reduction by the characteristic polynomial p*
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FOR i := 14 downto 8:
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p := 0x11B << (i-8)
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*0x11B = 0000_0001_0001_1011 in binary*
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IF tword.bit[i]:
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tword := tword XOR p
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return tword.byte[0]
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</pre>
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<h4 id="vgf2p8mulb-dest--src1--src2--evex-encoded-version-">VGF2P8MULB dest, src1, src2 (EVEX Encoded Version)<a class="anchor" href="#vgf2p8mulb-dest--src1--src2--evex-encoded-version-">
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¶
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</a></h4>
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<pre>(KL, VL) = (16, 128), (32, 256), (64, 512)
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FOR j := 0 TO KL-1:
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IF k1[j] OR *no writemask*:
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DEST.byte[j] := gf2p8mul_byte(SRC1.byte[j], SRC2.byte[j])
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ELSE iF *zeroing*:
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DEST.byte[j] := 0
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* ELSE DEST.byte[j] remains unchanged*
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DEST[MAX_VL-1:VL] := 0
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</pre>
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<h4 id="vgf2p8mulb-dest--src1--src2--128b-and-256b-vex-encoded-versions-">VGF2P8MULB dest, src1, src2 (128b and 256b VEX Encoded Versions)<a class="anchor" href="#vgf2p8mulb-dest--src1--src2--128b-and-256b-vex-encoded-versions-">
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¶
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</a></h4>
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<pre>(KL, VL) = (16, 128), (32, 256)
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FOR j := 0 TO KL-1:
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DEST.byte[j] := gf2p8mul_byte(SRC1.byte[j], SRC2.byte[j])
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DEST[MAX_VL-1:VL] := 0
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</pre>
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<h4 id="gf2p8mulb-srcdest--src1--128b-sse-encoded-version-">GF2P8MULB srcdest, src1 (128b SSE Encoded Version)<a class="anchor" href="#gf2p8mulb-srcdest--src1--128b-sse-encoded-version-">
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¶
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</a></h4>
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<pre>FOR j := 0 TO 15:
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SRCDEST.byte[j] :=gf2p8mul_byte(SRCDEST.byte[j], SRC1.byte[j])
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</pre>
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<h3 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h3>
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<pre>(V)GF2P8MULB __m128i _mm_gf2p8mul_epi8(__m128i, __m128i);
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</pre>
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<pre>(V)GF2P8MULB __m128i _mm_mask_gf2p8mul_epi8(__m128i, __mmask16, __m128i, __m128i);
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</pre>
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<pre>(V)GF2P8MULB __m128i _mm_maskz_gf2p8mul_epi8(__mmask16, __m128i, __m128i);
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</pre>
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<pre>VGF2P8MULB __m256i _mm256_gf2p8mul_epi8(__m256i, __m256i);
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</pre>
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<pre>VGF2P8MULB __m256i _mm256_mask_gf2p8mul_epi8(__m256i, __mmask32, __m256i, __m256i);
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</pre>
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<pre>VGF2P8MULB __m256i _mm256_maskz_gf2p8mul_epi8(__mmask32, __m256i, __m256i);
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</pre>
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<pre>VGF2P8MULB __m512i _mm512_gf2p8mul_epi8(__m512i, __m512i);
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</pre>
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<pre>VGF2P8MULB __m512i _mm512_mask_gf2p8mul_epi8(__m512i, __mmask64, __m512i, __m512i);
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</pre>
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<pre>VGF2P8MULB __m512i _mm512_maskz_gf2p8mul_epi8(__mmask64, __m512i, __m512i);
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</pre>
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<h3 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h3>
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<p>None.</p>
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<h3 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h3>
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<p>Legacy-encoded and VEX-encoded: See <span class="not-imported">Table 2-21</span>, “Type 4 Class Exception Conditions.”</p>
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<p>EVEX-encoded: See <span class="not-imported">Table 2-49</span>, “Type E4 Class Exception Conditions.”</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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