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117 lines
5.7 KiB
HTML
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>EXTRACTPS
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— Extract Packed Floating-Point Values</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>EXTRACTPS
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— Extract Packed Floating-Point Values</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op / En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>66 0F 3A 17 /r ib EXTRACTPS reg/m32, xmm1, imm8</td>
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<td>A</td>
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<td>VV</td>
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<td>SSE4_1</td>
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<td>Extract one single precision floating-point value from xmm1 at the offset specified by imm8 and store the result in reg or m32. Zero extend the results in 64-bit register if applicable.</td></tr>
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<tr>
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<td>VEX.128.66.0F3A.WIG 17 /r ib VEXTRACTPS reg/m32, xmm1, imm8</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Extract one single precision floating-point value from xmm1 at the offset specified by imm8 and store the result in reg or m32. Zero extend the results in 64-bit register if applicable.</td></tr>
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<tr>
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<td>EVEX.128.66.0F3A.WIG 17 /r ib VEXTRACTPS reg/m32, xmm1, imm8</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX512F</td>
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<td>Extract one single precision floating-point value from xmm1 at the offset specified by imm8 and store the result in reg or m32. Zero extend the results in 64-bit register if applicable.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple Type</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>N/A</td>
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<td>ModRM:r/m (w)</td>
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<td>ModRM:reg (r)</td>
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<td>imm8</td>
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<td>N/A</td></tr>
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<tr>
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<td>B</td>
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<td>Tuple1 Scalar</td>
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<td>ModRM:r/m (w)</td>
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<td>ModRM:reg (r)</td>
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<td>imm8</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Extracts a single precision floating-point value from the source operand (second operand) at the 32-bit offset specified from imm8. Immediate bits higher than the most significant offset for the vector length are ignored.</p>
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<p>The extracted single precision floating-point value is stored in the low 32-bits of the destination operand</p>
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<p>In 64-bit mode, destination register operand has default operand size of 64 bits. The upper 32-bits of the register are filled with zero. REX.W is ignored.</p>
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<p>VEX.128 and EVEX encoded version: When VEX.W1 or EVEX.W1 form is used in 64-bit mode with a general purpose register (GPR) as a destination operand, the packed single quantity is zero extended to 64 bits.</p>
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<p>VEX.vvvv/EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.</p>
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<p>128-bit Legacy SSE version: When a REX.W prefix is used in 64-bit mode with a general purpose register (GPR) as a destination operand, the packed single quantity is zero extended to 64 bits.</p>
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<p>The source register is an XMM register. Imm8[1:0] determine the starting DWORD offset from which to extract the 32-bit floating-point value.</p>
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<p>If VEXTRACTPS is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will cause an #UD exception.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<h3 id="vextractps--evex-and-vex-128-encoded-version-">VEXTRACTPS (EVEX and VEX.128 Encoded Version)<a class="anchor" href="#vextractps--evex-and-vex-128-encoded-version-">
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¶
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</a></h3>
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<pre>SRC_OFFSET := IMM8[1:0]
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IF (64-Bit Mode and DEST is register)
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DEST[31:0] := (SRC[127:0] >> (SRC_OFFSET*32)) AND 0FFFFFFFFh
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DEST[63:32] := 0
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ELSE
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DEST[31:0] := (SRC[127:0] >> (SRC_OFFSET*32)) AND 0FFFFFFFFh
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FI
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</pre>
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<h3 id="extractps--128-bit-legacy-sse-version-">EXTRACTPS (128-bit Legacy SSE Version)<a class="anchor" href="#extractps--128-bit-legacy-sse-version-">
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¶
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</a></h3>
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<pre>SRC_OFFSET := IMM8[1:0]
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IF (64-Bit Mode and DEST is register)
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DEST[31:0] := (SRC[127:0] >> (SRC_OFFSET*32)) AND 0FFFFFFFFh
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DEST[63:32] := 0
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ELSE
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DEST[31:0] := (SRC[127:0] >> (SRC_OFFSET*32)) AND 0FFFFFFFFh
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FI
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</pre>
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<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h2>
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<pre>EXTRACTPS int _mm_extract_ps (__m128 a, const int nidx);
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</pre>
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<h2 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h2>
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<p>VEX-encoded instructions, see <span class="not-imported">Table 2-22</span>, “Type 5 Class Exception Conditions.”</p>
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<p>EVEX-encoded instructions, see <span class="not-imported">Table 2-57</span>, “Type E9NF Class Exception Conditions.”</p>
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<p>Additionally:</p>
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<table>
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<tr>
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<td>#UD</td>
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<td>IF VEX.L = 0.</td></tr>
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<tr>
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<td>#UD</td>
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<td>If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.</td></tr></table><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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