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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>CVTDQ2PS
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— Convert Packed Doubleword Integers to Packed Single Precision Floating-PointValues</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>CVTDQ2PS
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— Convert Packed Doubleword Integers to Packed Single Precision Floating-PointValues</h1>
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<table>
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<tr>
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<th>Opcode Instruction</th>
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<th>Op / En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>NP 0F 5B /r CVTDQ2PS xmm1, xmm2/m128</td>
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<td>A</td>
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<td>V/V</td>
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<td>SSE2</td>
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<td>Convert four packed signed doubleword integers from xmm2/mem to four packed single precision floating-point values in xmm1.</td></tr>
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<tr>
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<td>VEX.128.0F.WIG 5B /r VCVTDQ2PS xmm1, xmm2/m128</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Convert four packed signed doubleword integers from xmm2/mem to four packed single precision floating-point values in xmm1.</td></tr>
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<tr>
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<td>VEX.256.0F.WIG 5B /r VCVTDQ2PS ymm1, ymm2/m256</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Convert eight packed signed doubleword integers from ymm2/mem to eight packed single precision floating-point values in ymm1.</td></tr>
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<tr>
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<td>EVEX.128.0F.W0 5B /r VCVTDQ2PS xmm1 {k1}{z}, xmm2/m128/m32bcst</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX512VL AVX512F</td>
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<td>Convert four packed signed doubleword integers from xmm2/m128/m32bcst to four packed single precision floating-point values in xmm1with writemask k1.</td></tr>
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<tr>
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<td>EVEX.256.0F.W0 5B /r VCVTDQ2PS ymm1 {k1}{z}, ymm2/m256/m32bcst</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX512VL AVX512F</td>
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<td>Convert eight packed signed doubleword integers from ymm2/m256/m32bcst to eight packed single precision floating-point values in ymm1with writemask k1.</td></tr>
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<tr>
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<td>EVEX.512.0F.W0 5B /r VCVTDQ2PS zmm1 {k1}{z}, zmm2/m512/m32bcst{er}</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX512F</td>
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<td>Convert sixteen packed signed doubleword integers from zmm2/m512/m32bcst to sixteen packed single precision floating-point values in zmm1with writemask k1.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple Type</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>N/A</td>
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<td>ModRM:reg (w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr>
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<tr>
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<td>B</td>
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<td>Full</td>
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<td>ModRM:reg (w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Converts four, eight or sixteen packed signed doubleword integers in the source operand to four, eight or sixteen packed single precision floating-point values in the destination operand.</p>
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<p>EVEX encoded versions: The source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1.</p>
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<p>VEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination operand is a YMM register. Bits (MAXVL-1:256) of the corresponding register destination are zeroed.</p>
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<p>VEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination operand is a XMM register. The upper bits (MAXVL-1:128) of the corresponding register destination are zeroed.</p>
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<p>128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination operand is an XMM register. The upper Bits (MAXVL-1:128) of the corresponding register destination are unmodified.</p>
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<p>VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<h3 id="vcvtdq2ps--evex-encoded-versions--when-src-operand-is-a-register">VCVTDQ2PS (EVEX Encoded Versions) When SRC Operand is a Register<a class="anchor" href="#vcvtdq2ps--evex-encoded-versions--when-src-operand-is-a-register">
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¶
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</a></h3>
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<pre>(KL, VL) = (4, 128), (8, 256), (16, 512)
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IF (VL = 512) AND (EVEX.b = 1)
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THEN
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SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC); ; refer to <span class="not-imported">Table 15-4</span> in the Intel<sup>®</sup> 64 and IA-32 Architectures
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Software Developer’s Manual, Volume 1
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ELSE
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SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC); ; refer to <span class="not-imported">Table 15-4</span> in the Intel<sup>®</sup> 64 and IA-32 Architectures
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Software Developer’s Manual, Volume 1
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FI;
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FOR j := 0 TO KL-1
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i := j * 32
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IF k1[j] OR *no writemask*
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THEN DEST[i+31:i] :=
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Convert_Integer_To_Single_Precision_Floating_Point(SRC[i+31:i])
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ELSE
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IF *merging-masking* ; merging-masking
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THEN *DEST[i+31:i] remains unchanged*
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ELSE ; zeroing-masking
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DEST[i+31:i] := 0
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FI
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FI;
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ENDFOR
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DEST[MAXVL-1:VL] := 0
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</pre>
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<h3 id="vcvtdq2ps--evex-encoded-versions--when-src-operand-is-a-memory-source">VCVTDQ2PS (EVEX Encoded Versions) When SRC Operand is a Memory Source<a class="anchor" href="#vcvtdq2ps--evex-encoded-versions--when-src-operand-is-a-memory-source">
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¶
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</a></h3>
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<pre>(KL, VL) = (4, 128), (8, 256), (16, 512)
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FOR j := 0 TO KL-1
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i := j * 32
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IF k1[j] OR *no writemask*
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THEN
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IF (EVEX.b = 1)
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THEN
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DEST[i+31:i] :=
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Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0])
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ELSE
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DEST[i+31:i] :=
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Convert_Integer_To_Single_Precision_Floating_Point(SRC[i+31:i])
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FI;
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ELSE
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IF *merging-masking* ; merging-masking
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THEN *DEST[i+31:i] remains unchanged*
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ELSE ; zeroing-masking
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DEST[i+31:i] := 0
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FI
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FI;
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ENDFOR
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DEST[MAXVL-1:VL] := 0
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</pre>
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<h3 id="vcvtdq2ps--vex-256-encoded-version-">VCVTDQ2PS (VEX.256 Encoded Version)<a class="anchor" href="#vcvtdq2ps--vex-256-encoded-version-">
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¶
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</a></h3>
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<pre>DEST[31:0] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0])
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DEST[63:32] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32])
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DEST[95:64] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[95:64])
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DEST[127:96] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[127:96)
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DEST[159:128] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[159:128])
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DEST[191:160] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[191:160])
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DEST[223:192] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[223:192])
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DEST[255:224] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[255:224)
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DEST[MAXVL-1:256] := 0
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</pre>
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<h3 id="vcvtdq2ps--vex-128-encoded-version-">VCVTDQ2PS (VEX.128 Encoded Version)<a class="anchor" href="#vcvtdq2ps--vex-128-encoded-version-">
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¶
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</a></h3>
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<pre>DEST[31:0] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0])
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DEST[63:32] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32])
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DEST[95:64] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[95:64])
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DEST[127:96] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[127z:96)
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DEST[MAXVL-1:128] := 0
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</pre>
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<h3 id="cvtdq2ps--128-bit-legacy-sse-version-">CVTDQ2PS (128-bit Legacy SSE Version)<a class="anchor" href="#cvtdq2ps--128-bit-legacy-sse-version-">
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¶
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</a></h3>
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<pre>DEST[31:0] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0])
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DEST[63:32] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32])
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DEST[95:64] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[95:64])
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DEST[127:96] := Convert_Integer_To_Single_Precision_Floating_Point(SRC[127z:96)
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DEST[MAXVL-1:128] (unmodified)
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</pre>
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<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h2>
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<pre>VCVTDQ2PS __m512 _mm512_cvtepi32_ps( __m512i a);
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</pre>
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<pre>VCVTDQ2PS __m512 _mm512_mask_cvtepi32_ps( __m512 s, __mmask16 k, __m512i a);
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</pre>
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<pre>VCVTDQ2PS __m512 _mm512_maskz_cvtepi32_ps( __mmask16 k, __m512i a);
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</pre>
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<pre>VCVTDQ2PS __m512 _mm512_cvt_roundepi32_ps( __m512i a, int r);
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</pre>
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<pre>VCVTDQ2PS __m512 _mm512_mask_cvt_roundepi_ps( __m512 s, __mmask16 k, __m512i a, int r);
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</pre>
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<pre>VCVTDQ2PS __m512 _mm512_maskz_cvt_roundepi32_ps( __mmask16 k, __m512i a, int r);
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</pre>
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<pre>VCVTDQ2PS __m256 _mm256_mask_cvtepi32_ps( __m256 s, __mmask8 k, __m256i a);
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</pre>
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<pre>VCVTDQ2PS __m256 _mm256_maskz_cvtepi32_ps( __mmask8 k, __m256i a);
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</pre>
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<pre>VCVTDQ2PS __m128 _mm_mask_cvtepi32_ps( __m128 s, __mmask8 k, __m128i a);
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</pre>
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<pre>VCVTDQ2PS __m128 _mm_maskz_cvtepi32_ps( __mmask8 k, __m128i a);
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</pre>
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<pre>CVTDQ2PS __m256 _mm256_cvtepi32_ps (__m256i src)
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</pre>
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<pre>CVTDQ2PS __m128 _mm_cvtepi32_ps (__m128i src)
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</pre>
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<h2 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h2>
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<p>Precision.</p>
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<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h2>
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<p>VEX-encoded instructions, see <span class="not-imported">Table 2-19</span>, “Type 2 Class Exception Conditions.”</p>
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<p>EVEX-encoded instructions, see <span class="not-imported">Table 2-46</span>, “Type E2 Class Exception Conditions.”</p>
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<p>Additionally:</p>
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<table>
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<tr>
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<td>#UD</td>
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<td>If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.</td></tr></table><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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