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<!DOCTYPE html>
<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>GETSEC[CAPABILITIES]
— Report the SMX Capabilities</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>GETSEC[CAPABILITIES]
— Report the SMX Capabilities</h1>
<table>
<tr>
<th>Opcode</th>
<th>Instruction</th>
<th>Description</th></tr>
<tr>
<td>NP 0F 37 (EAX = 0)</td>
<td>GETSEC[CAPABILITIES]</td>
<td>Report the SMX capabilities. The capabilities index is input in EBX with the result returned in EAX.</td></tr></table>
<h2 id="description">Description<a class="anchor" href="#description">
</a></h2>
<p>The GETSEC[CAPABILITIES] function returns a bit vector of supported GETSEC leaf functions. The CAPABILITIES leaf of GETSEC is selected with EAX set to 0 at entry. EBX is used as the selector for returning the bit vector field in EAX. GETSEC[CAPABILITIES] may be executed at all privilege levels, but the CR4.SMXE bit must be set or an undefined opcode exception (#UD) is returned.</p>
<p>With EBX = 0 upon execution of GETSEC[CAPABILITIES], EAX returns the a bit vector representing status on the presence of a Intel<sup>®</sup> TXT-capable chipset and the first 30 available GETSEC leaf functions. The format of the returned bit vector is provided in <span class="not-imported">Table 7-3</span>.</p>
<p>If bit 0 is set to 1, then an Intel<sup>®</sup> TXT-capable chipset has been sampled present by the processor. If bits in the range of 1-30 are set, then the corresponding GETSEC leaf function is available. If the bit value at a given bit index is 0, then the GETSEC leaf function corresponding to that index is unsupported and attempted execution results in a #UD.</p>
<p>Bit 31 of EAX indicates if further leaf indexes are supported. If the Extended Leafs bit 31 is set, then additional leaf functions are accessed by repeating GETSEC[CAPABILITIES] with EBX incremented by one. When the most significant bit of EAX is not set, then additional GETSEC leaf functions are not supported; indexing EBX to a higher value results in EAX returning zero.</p>
<figure id="tbl-7-3">
<table>
<tr>
<th>Field</th>
<th>Bit position</th>
<th>Description</th></tr>
<tr>
<td>Chipset Present</td>
<td>0</td>
<td>Intel® TXT-capable chipset is present.</td></tr>
<tr>
<td>Undefined</td>
<td>1</td>
<td>Reserved</td></tr>
<tr>
<td>ENTERACCS</td>
<td>2</td>
<td>GETSEC[ENTERACCS] is available.</td></tr>
<tr>
<td>EXITAC</td>
<td>3</td>
<td>GETSEC[EXITAC] is available.</td></tr>
<tr>
<td>SENTER</td>
<td>4</td>
<td>GETSEC[SENTER] is available.</td></tr>
<tr>
<td>SEXIT</td>
<td>5</td>
<td>GETSEC[SEXIT] is available.</td></tr>
<tr>
<td>PARAMETERS</td>
<td>6</td>
<td>GETSEC[PARAMETERS] is available.</td></tr>
<tr>
<td>SMCTRL</td>
<td>7</td>
<td>GETSEC[SMCTRL] is available.</td></tr>
<tr>
<td>WAKEUP</td>
<td>8</td>
<td>GETSEC[WAKEUP] is available.</td></tr>
<tr>
<td>Undefined</td>
<td>30:9</td>
<td>Reserved</td></tr>
<tr>
<td>Extended Leafs</td>
<td>31</td>
<td>Reserved for extended information reporting of GETSEC capabilities.</td></tr></table>
<figcaption><span class="not-imported">Table 7-3</span>. GETSEC Capability Result Encoding (EBX = 0)</figcaption></figure>
<h2 id="operation">Operation<a class="anchor" href="#operation">
</a></h2>
<pre>IF (CR4.SMXE=0)
THEN #UD;
ELSIF (in VMX non-root operation)
THEN VM Exit (reason=”GETSEC instruction”);
IF (EBX=0) THEN
BitVector := 0;
IF (TXT chipset present)
BitVector[Chipset present] := 1;
IF (ENTERACCS Available)
THEN BitVector[ENTERACCS] := 1;
IF (EXITAC Available)
THEN BitVector[EXITAC] := 1;
IF (SENTER Available)
THEN BitVector[SENTER] := 1;
IF (SEXIT Available)
THEN BitVector[SEXIT] := 1;
IF (PARAMETERS Available)
THEN BitVector[PARAMETERS] := 1;
IF (SMCTRL Available)
THEN BitVector[SMCTRL] := 1;
IF (WAKEUP Available)
THEN BitVector[WAKEUP] := 1;
EAX := BitVector;
ELSE
EAX := 0;
END;;
</pre>
<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
</a></h2>
<p>None.</p>
<h2 id="use-of-prefixes">Use of Prefixes<a class="anchor" href="#use-of-prefixes">
</a></h2>
<p>LOCK Causes #UD.</p>
<p>REP* Cause #UD (includes REPNE/REPNZ and REP/REPE/REPZ).</p>
<p>Operand size Causes #UD.</p>
<p>NP 66/F2/F3 prefixes are not allowed.</p>
<p>Segmentoverrides Ignored.</p>
<p>Address size Ignored.</p>
<p>REX Ignored.</p>
<h2 class="exceptions" id="protected-mode-exceptions">Protected Mode Exceptions<a class="anchor" href="#protected-mode-exceptions">
</a></h2>
<table>
<tr>
<td>#UD</td>
<td>If CR4.SMXE = 0.</td></tr></table>
<h2 class="exceptions" id="real-address-mode-exceptions">Real-Address Mode Exceptions<a class="anchor" href="#real-address-mode-exceptions">
</a></h2>
<table>
<tr>
<td>#UD</td>
<td>If CR4.SMXE = 0.</td></tr></table>
<h2 class="exceptions" id="virtual-8086-mode-exceptions">Virtual-8086 Mode Exceptions<a class="anchor" href="#virtual-8086-mode-exceptions">
</a></h2>
<table>
<tr>
<td>#UD</td>
<td>If CR4.SMXE = 0.</td></tr></table>
<h2 class="exceptions" id="compatibility-mode-exceptions">Compatibility Mode Exceptions<a class="anchor" href="#compatibility-mode-exceptions">
</a></h2>
<table>
<tr>
<td>#UD</td>
<td>If CR4.SMXE = 0.</td></tr></table>
<h2 class="exceptions" id="64-bit-mode-exceptions">64-Bit Mode Exceptions<a class="anchor" href="#64-bit-mode-exceptions">
</a></h2>
<table>
<tr>
<td>#UD</td>
<td>If CR4.SMXE = 0.</td></tr></table>
<h2 id="vm-exit-condition">VM-exit Condition<a class="anchor" href="#vm-exit-condition">
</a></h2>
<p>Reason (GETSEC) If in VMX non-root operation.</p><footer><p>
This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
</p></footer></body></html>
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