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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>ANDNPD
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— Bitwise Logical AND NOT of Packed Double Precision Floating-Point Values</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>ANDNPD
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— Bitwise Logical AND NOT of Packed Double Precision Floating-Point Values</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op / En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>66 0F 55 /r ANDNPD xmm1, xmm2/m128</td>
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<td>A</td>
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<td>V/V</td>
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<td>SSE2</td>
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<td>Return the bitwise logical AND NOT of packed double precision floating-point values in xmm1 and xmm2/mem.</td></tr>
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<tr>
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<td>VEX.128.66.0F 55 /r VANDNPD xmm1, xmm2, xmm3/m128</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Return the bitwise logical AND NOT of packed double precision floating-point values in xmm2 and xmm3/mem.</td></tr>
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<tr>
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<td>VEX.256.66.0F 55/r VANDNPD ymm1, ymm2, ymm3/m256</td>
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<td>B</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Return the bitwise logical AND NOT of packed double precision floating-point values in ymm2 and ymm3/mem.</td></tr>
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<tr>
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<td>EVEX.128.66.0F.W1 55 /r VANDNPD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst</td>
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<td>C</td>
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<td>V/V</td>
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<td>AVX512VL AVX512DQ</td>
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<td>Return the bitwise logical AND NOT of packed double precision floating-point values in xmm2 and xmm3/m128/m64bcst subject to writemask k1.</td></tr>
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<tr>
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<td>EVEX.256.66.0F.W1 55 /r VANDNPD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst</td>
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<td>C</td>
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<td>V/V</td>
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<td>AVX512VL AVX512DQ</td>
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<td>Return the bitwise logical AND NOT of packed double precision floating-point values in ymm2 and ymm3/m256/m64bcst subject to writemask k1.</td></tr>
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<tr>
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<td>EVEX.512.66.0F.W1 55 /r VANDNPD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst</td>
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<td>C</td>
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<td>V/V</td>
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<td>AVX512DQ</td>
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<td>Return the bitwise logical AND NOT of packed double precision floating-point values in zmm2 and zmm3/m512/m64bcst subject to writemask k1.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple Type</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>N/A</td>
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<td>ModRM:reg (r, w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr>
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<tr>
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<td>B</td>
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<td>N/A</td>
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<td>ModRM:reg (w)</td>
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<td>VEX.vvvv (r)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td></tr>
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<tr>
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<td>C</td>
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<td>Full</td>
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<td>ModRM:reg (w)</td>
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<td>EVEX.vvvv (r)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Performs a bitwise logical AND NOT of the two, four or eight packed double precision floating-point values from the first source operand and the second source operand, and stores the result in the destination operand.</p>
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<p>EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1.</p>
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<p>VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAXVL-1:256) of the corresponding ZMM register destination are zeroed.</p>
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<p>VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding ZMM register destination are zeroed.</p>
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<p>128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding register destination are unmodified.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<h3 id="vandnpd--evex-encoded-versions-">VANDNPD (EVEX Encoded Versions)<a class="anchor" href="#vandnpd--evex-encoded-versions-">
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¶
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</a></h3>
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<pre>(KL, VL) = (2, 128), (4, 256), (8, 512)
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FOR j := 0 TO KL-1
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i := j * 64
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IF k1[j] OR *no writemask*
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IF (EVEX.b == 1) AND (SRC2 *is memory*)
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THEN
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DEST[i+63:i] := (NOT(SRC1[i+63:i])) BITWISE AND SRC2[63:0]
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ELSE
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DEST[i+63:i] := (NOT(SRC1[i+63:i])) BITWISE AND SRC2[i+63:i]
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FI;
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ELSE
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IF *merging-masking* ; merging-masking
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THEN *DEST[i+63:i] remains unchanged*
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ELSE ; zeroing-masking
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DEST[i+63:i] = 0
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FI;
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FI;
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ENDFOR
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DEST[MAXVL-1:VL] := 0
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</pre>
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<h3 id="vandnpd--vex-256-encoded-version-">VANDNPD (VEX.256 Encoded Version)<a class="anchor" href="#vandnpd--vex-256-encoded-version-">
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¶
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</a></h3>
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<pre>DEST[63:0] := (NOT(SRC1[63:0])) BITWISE AND SRC2[63:0]
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DEST[127:64] := (NOT(SRC1[127:64])) BITWISE AND SRC2[127:64]
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DEST[191:128] := (NOT(SRC1[191:128])) BITWISE AND SRC2[191:128]
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DEST[255:192] := (NOT(SRC1[255:192])) BITWISE AND SRC2[255:192]
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DEST[MAXVL-1:256] := 0
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</pre>
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<h3 id="vandnpd--vex-128-encoded-version-">VANDNPD (VEX.128 Encoded Version)<a class="anchor" href="#vandnpd--vex-128-encoded-version-">
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¶
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</a></h3>
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<pre>DEST[63:0] := (NOT(SRC1[63:0])) BITWISE AND SRC2[63:0]
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DEST[127:64] := (NOT(SRC1[127:64])) BITWISE AND SRC2[127:64]
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DEST[MAXVL-1:128] := 0
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</pre>
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<h3 id="andnpd--128-bit-legacy-sse-version-">ANDNPD (128-bit Legacy SSE Version)<a class="anchor" href="#andnpd--128-bit-legacy-sse-version-">
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¶
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</a></h3>
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<pre>DEST[63:0] := (NOT(DEST[63:0])) BITWISE AND SRC[63:0]
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DEST[127:64] := (NOT(DEST[127:64])) BITWISE AND SRC[127:64]
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DEST[MAXVL-1:128] (Unmodified)
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</pre>
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<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h2>
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<pre>VANDNPD __m512d _mm512_andnot_pd (__m512d a, __m512d b);
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</pre>
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<pre>VANDNPD __m512d _mm512_mask_andnot_pd (__m512d s, __mmask8 k, __m512d a, __m512d b);
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</pre>
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<pre>VANDNPD __m512d _mm512_maskz_andnot_pd (__mmask8 k, __m512d a, __m512d b);
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</pre>
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<pre>VANDNPD __m256d _mm256_mask_andnot_pd (__m256d s, __mmask8 k, __m256d a, __m256d b);
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</pre>
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<pre>VANDNPD __m256d _mm256_maskz_andnot_pd (__mmask8 k, __m256d a, __m256d b);
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</pre>
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<pre>VANDNPD __m128d _mm_mask_andnot_pd (__m128d s, __mmask8 k, __m128d a, __m128d b);
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</pre>
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<pre>VANDNPD __m128d _mm_maskz_andnot_pd (__mmask8 k, __m128d a, __m128d b);
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</pre>
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<pre>VANDNPD __m256d _mm256_andnot_pd (__m256d a, __m256d b);
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</pre>
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<pre>ANDNPD __m128d _mm_andnot_pd (__m128d a, __m128d b);
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</pre>
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<h2 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h2>
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<p>VEX-encoded instruction, see <span class="not-imported">Table 2-21</span>, “Type 4 Class Exception Conditions.”</p>
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<p>EVEX-encoded instruction, see <span class="not-imported">Table 2-49</span>, “Type E4 Class Exception Conditions.”</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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