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313 lines
10 KiB
HTML
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>ADC
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— Add With Carry</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>ADC
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— Add With Carry</h1>
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<table>
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<tr>
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<th>Opcode</th>
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<th>Instruction</th>
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<th>Op/En</th>
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<th>64-bit Mode</th>
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<th>Compat/Leg Mode</th>
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<th>Description</th></tr>
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<tr>
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<td>14 ib</td>
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<td>ADC AL, imm8</td>
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<td>I</td>
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<td>Valid</td>
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<td>Valid</td>
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<td>Add with carry imm8 to AL.</td></tr>
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<tr>
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<td>15 iw</td>
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<td>ADC AX, imm16</td>
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<td>I</td>
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<td>Valid</td>
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<td>Valid</td>
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<td>Add with carry imm16 to AX.</td></tr>
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<tr>
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<td>15 id</td>
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<td>ADC EAX, imm32</td>
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<td>I</td>
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<td>Valid</td>
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<td>Valid</td>
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<td>Add with carry imm32 to EAX.</td></tr>
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<tr>
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<td>REX.W + 15 id</td>
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<td>ADC RAX, imm32</td>
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<td>I</td>
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<td>Valid</td>
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<td>N.E.</td>
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<td>Add with carry imm32 sign extended to 64-bits to RAX.</td></tr>
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<tr>
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<td>80 /2 ib</td>
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<td>ADC r/m8, imm8</td>
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<td>MI</td>
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<td>Valid</td>
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<td>Valid</td>
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<td>Add with carry imm8 to r/m8.</td></tr>
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<tr>
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<td>REX + 80 /2 ib</td>
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<td>ADC r/m8<sup>*</sup>, imm8</td>
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<td>MI</td>
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<td>Valid</td>
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<td>N.E.</td>
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<td>Add with carry imm8 to r/m8.</td></tr>
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<tr>
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<td>81 /2 iw</td>
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<td>ADC r/m16, imm16</td>
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<td>MI</td>
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<td>Valid</td>
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<td>Valid</td>
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<td>Add with carry imm16 to r/m16.</td></tr>
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<tr>
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<td>81 /2 id</td>
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<td>ADC r/m32, imm32</td>
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<td>MI</td>
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<td>Valid</td>
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<td>Valid</td>
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<td>Add with CF imm32 to r/m32.</td></tr>
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<tr>
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<td>REX.W + 81 /2 id</td>
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<td>ADC r/m64, imm32</td>
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<td>MI</td>
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<td>Valid</td>
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<td>N.E.</td>
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<td>Add with CF imm32 sign extended to 64-bits to r/m64.</td></tr>
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<tr>
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<td>83 /2 ib</td>
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<td>ADC r/m16, imm8</td>
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<td>MI</td>
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<td>Valid</td>
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<td>Valid</td>
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<td>Add with CF sign-extended imm8 to r/m16.</td></tr>
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<tr>
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<td>83 /2 ib</td>
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<td>ADC r/m32, imm8</td>
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<td>MI</td>
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<td>Valid</td>
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<td>Valid</td>
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<td>Add with CF sign-extended imm8 into r/m32.</td></tr>
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<tr>
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<td>REX.W + 83 /2 ib</td>
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<td>ADC r/m64, imm8</td>
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<td>MI</td>
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<td>Valid</td>
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<td>N.E.</td>
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<td>Add with CF sign-extended imm8 into r/m64.</td></tr>
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<tr>
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<td>10 /r</td>
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<td>ADC r/m8, r8</td>
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<td>MR</td>
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<td>Valid</td>
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<td>Valid</td>
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<td>Add with carry byte register to r/m8.</td></tr>
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<tr>
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<td>REX + 10 /r</td>
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<td>ADC r/m8<sup>*</sup>, r8<sup>*</sup></td>
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<td>MR</td>
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<td>Valid</td>
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<td>N.E.</td>
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<td>Add with carry byte register to r/m64.</td></tr>
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<tr>
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<td>11 /r</td>
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<td>ADC r/m16, r16</td>
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<td>MR</td>
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<td>Valid</td>
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<td>Valid</td>
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<td>Add with carry r16 to r/m16.</td></tr>
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<tr>
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<td>11 /r</td>
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<td>ADC r/m32, r32</td>
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<td>MR</td>
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<td>Valid</td>
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<td>Valid</td>
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<td>Add with CF r32 to r/m32.</td></tr>
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<tr>
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<td>REX.W + 11 /r</td>
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<td>ADC r/m64, r64</td>
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<td>MR</td>
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<td>Valid</td>
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<td>N.E.</td>
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<td>Add with CF r64 to r/m64.</td></tr>
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<tr>
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<td>12 /r</td>
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<td>ADC r8, r/m8</td>
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<td>RM</td>
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<td>Valid</td>
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<td>Valid</td>
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<td>Add with carry r/m8 to byte register.</td></tr>
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<tr>
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<td>REX + 12 /r</td>
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<td>ADC r8<sup>*</sup>, r/m8<sup>*</sup></td>
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<td>RM</td>
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<td>Valid</td>
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<td>N.E.</td>
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<td>Add with carry r/m64 to byte register.</td></tr>
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<tr>
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<td>13 /r</td>
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<td>ADC r16, r/m16</td>
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<td>RM</td>
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<td>Valid</td>
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<td>Valid</td>
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<td>Add with carry r/m16 to r16.</td></tr>
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<tr>
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<td>13 /r</td>
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<td>ADC r32, r/m32</td>
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<td>RM</td>
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<td>Valid</td>
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<td>Valid</td>
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<td>Add with CF r/m32 to r32.</td></tr>
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<tr>
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<td>REX.W + 13 /r</td>
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<td>ADC r64, r/m64</td>
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<td>RM</td>
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<td>Valid</td>
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<td>N.E.</td>
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<td>Add with CF r/m64 to r64.</td></tr></table>
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<blockquote>
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<p>*In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.</p></blockquote>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>RM</td>
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<td>ModRM:reg (r, w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr>
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<tr>
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<td>MR</td>
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<td>ModRM:r/m (r, w)</td>
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<td>ModRM:reg (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr>
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<tr>
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<td>MI</td>
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<td>ModRM:r/m (r, w)</td>
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<td>imm8/16/32</td>
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<td>N/A</td>
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<td>N/A</td></tr>
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<tr>
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<td>I</td>
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<td>AL/AX/EAX/RAX</td>
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<td>imm8/16/32</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Adds the destination operand (first operand), the source operand (second operand), and the carry (CF) flag and stores the result in the destination operand. The destination operand can be a register or a memory location; the source operand can be an immediate, a register, or a memory location. (However, two memory operands cannot be used in one instruction.) The state of the CF flag represents a carry from a previous addition. When an immediate value is used as an operand, it is sign-extended to the length of the destination operand format.</p>
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<p>The ADC instruction does not distinguish between signed or unsigned operands. Instead, the processor evaluates the result for both data types and sets the OF and CF flags to indicate a carry in the signed or unsigned result, respectively. The SF flag indicates the sign of the signed result.</p>
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<p>The ADC instruction is usually executed as part of a multibyte or multiword addition in which an ADD instruction is followed by an ADC instruction.</p>
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<p>This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.</p>
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<p>In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<pre>DEST := DEST + SRC + CF;
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</pre>
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<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h2>
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<pre>ADC extern unsigned char _addcarry_u8(unsigned char c_in, unsigned char src1, unsigned char src2, unsigned char *sum_out);
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</pre>
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<pre>ADC extern unsigned char _addcarry_u16(unsigned char c_in, unsigned short src1, unsigned short src2, unsigned short *sum_out);
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</pre>
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<pre>ADC extern unsigned char _addcarry_u32(unsigned char c_in, unsigned int src1, unsigned char int, unsigned int *sum_out);
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</pre>
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<pre>ADC extern unsigned char _addcarry_u64(unsigned char c_in, unsigned __int64 src1, unsigned __int64 src2, unsigned __int64 *sum_out);
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</pre>
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<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
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¶
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</a></h2>
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<p>The OF, SF, ZF, AF, CF, and PF flags are set according to the result.</p>
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<h2 class="exceptions" id="protected-mode-exceptions">Protected Mode Exceptions<a class="anchor" href="#protected-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td rowspan="3">#GP(0)</td>
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<td>If the destination is located in a non-writable segment.</td></tr>
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<tr>
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<td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
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<tr>
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<td>If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector.</td></tr>
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<tr>
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<td>#SS(0)</td>
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<td>If a memory operand effective address is outside the SS segment limit.</td></tr>
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<tr>
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<td>#PF(fault-code)</td>
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<td>If a page fault occurs.</td></tr>
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<tr>
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<td>#AC(0)</td>
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<td>If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.</td></tr>
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<tr>
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<td>#UD</td>
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<td>If the LOCK prefix is used but the destination is not a memory operand.</td></tr></table>
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<h2 class="exceptions" id="real-address-mode-exceptions">Real-Address Mode Exceptions<a class="anchor" href="#real-address-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td>#GP</td>
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<td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
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<tr>
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<td>#SS</td>
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<td>If a memory operand effective address is outside the SS segment limit.</td></tr>
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<tr>
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<td>#UD</td>
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<td>If the LOCK prefix is used but the destination is not a memory operand.</td></tr></table>
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<h2 class="exceptions" id="virtual-8086-mode-exceptions">Virtual-8086 Mode Exceptions<a class="anchor" href="#virtual-8086-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td>#GP(0)</td>
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<td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
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<tr>
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<td>#SS(0)</td>
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<td>If a memory operand effective address is outside the SS segment limit.</td></tr>
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<tr>
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<td>#PF(fault-code)</td>
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<td>If a page fault occurs.</td></tr>
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<tr>
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<td>#AC(0)</td>
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<td>If alignment checking is enabled and an unaligned memory reference is made.</td></tr>
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<tr>
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<td>#UD</td>
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<td>If the LOCK prefix is used but the destination is not a memory operand.</td></tr></table>
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<h2 class="exceptions" id="compatibility-mode-exceptions">Compatibility Mode Exceptions<a class="anchor" href="#compatibility-mode-exceptions">
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¶
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</a></h2>
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<p>Same exceptions as in protected mode.</p>
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<h2 class="exceptions" id="64-bit-mode-exceptions">64-Bit Mode Exceptions<a class="anchor" href="#64-bit-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td>#SS(0)</td>
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<td>If a memory address referencing the SS segment is in a non-canonical form.</td></tr>
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<tr>
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<td>#GP(0)</td>
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<td>If the memory address is in a non-canonical form.</td></tr>
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<tr>
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<td>#PF(fault-code)</td>
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<td>If a page fault occurs.</td></tr>
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<tr>
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<td>#AC(0)</td>
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<td>If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.</td></tr>
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<tr>
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<td>#UD</td>
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<td>If the LOCK prefix is used but the destination is not a memory operand.</td></tr></table><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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