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290 lines
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>VPMOVQW/VPMOVSQW/VPMOVUSQW
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— Down Convert QWord to Word</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>VPMOVQW/VPMOVSQW/VPMOVUSQW
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— Down Convert QWord to Word</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op / En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>EVEX.128.F3.0F38.W0 34 /r VPMOVQW xmm1/m32 {k1}{z}, xmm2</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512VL AVX512F</td>
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<td>Converts 2 packed quad-word integers from xmm2 into 2 packed word integers in xmm1/m32 with truncation under writemask k1.</td></tr>
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<tr>
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<td>EVEX.128.F3.0F38.W0 24 /r VPMOVSQW xmm1/m32 {k1}{z}, xmm2</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512VL AVX512F</td>
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<td>Converts 8 packed signed quad-word integers from zmm2 into 8 packed signed word integers in xmm1/m32 using signed saturation under writemask k1.</td></tr>
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<tr>
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<td>EVEX.128.F3.0F38.W0 14 /r VPMOVUSQW xmm1/m32 {k1}{z}, xmm2</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512VL AVX512F</td>
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<td>Converts 2 packed unsigned quad-word integers from xmm2 into 2 packed unsigned word integers in xmm1/m32 using unsigned saturation under writemask k1.</td></tr>
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<tr>
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<td>EVEX.256.F3.0F38.W0 34 /r VPMOVQW xmm1/m64 {k1}{z}, ymm2</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512VL AVX512F</td>
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<td>Converts 4 packed quad-word integers from ymm2 into 4 packed word integers in xmm1/m64 with truncation under writemask k1.</td></tr>
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<tr>
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<td>EVEX.256.F3.0F38.W0 24 /r VPMOVSQW xmm1/m64 {k1}{z}, ymm2</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512VL AVX512F</td>
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<td>Converts 4 packed signed quad-word integers from ymm2 into 4 packed signed word integers in xmm1/m64 using signed saturation under writemask k1.</td></tr>
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<tr>
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<td>EVEX.256.F3.0F38.W0 14 /r VPMOVUSQW xmm1/m64 {k1}{z}, ymm2</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512VL AVX512F</td>
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<td>Converts 4 packed unsigned quad-word integers from ymm2 into 4 packed unsigned word integers in xmm1/m64 using unsigned saturation under writemask k1.</td></tr>
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<tr>
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<td>EVEX.512.F3.0F38.W0 34 /r VPMOVQW xmm1/m128 {k1}{z}, zmm2</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512F</td>
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<td>Converts 8 packed quad-word integers from zmm2 into 8 packed word integers in xmm1/m128 with truncation under writemask k1.</td></tr>
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<tr>
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<td>EVEX.512.F3.0F38.W0 24 /r VPMOVSQW xmm1/m128 {k1}{z}, zmm2</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512F</td>
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<td>Converts 8 packed signed quad-word integers from zmm2 into 8 packed signed word integers in xmm1/m128 using signed saturation under writemask k1.</td></tr>
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<tr>
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<td>EVEX.512.F3.0F38.W0 14 /r VPMOVUSQW xmm1/m128 {k1}{z}, zmm2</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512F</td>
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<td>Converts 8 packed unsigned quad-word integers from zmm2 into 8 packed unsigned word integers in xmm1/m128 using unsigned saturation under writemask k1.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple Type</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>Quarter Mem</td>
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<td>ModRM:r/m (w)</td>
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<td>ModRM:reg (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h3 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h3>
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<p>VPMOVQW down converts 64-bit integer elements in the source operand (the second operand) into packed words using truncation. VPMOVSQW converts signed 64-bit integers into packed signed words using signed saturation. VPMOVUSQW convert unsigned quad-word values into unsigned word values using unsigned saturation.</p>
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<p>The source operand is a ZMM/YMM/XMM register. The destination operand is a XMM register or a 128/64/32-bit memory location.</p>
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<p>Down-converted word elements are written to the destination operand (the first operand) from the least-significant word. Word elements of the destination operand are updated according to the writemask. Bits (MAXVL-1:128/64/32) of the register destination are zeroed.</p>
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<p>EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.</p>
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<h3 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h3>
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<h4 id="vpmovqw-instruction--evex-encoded-versions--when-dest-is-a-register">VPMOVQW instruction (EVEX encoded versions) when dest is a register<a class="anchor" href="#vpmovqw-instruction--evex-encoded-versions--when-dest-is-a-register">
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¶
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</a></h4>
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<pre>(KL, VL) = (2, 128), (4, 256), (8, 512)
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FOR j := 0 TO KL-1
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i := j * 16
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m := j * 64
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IF k1[j] OR *no writemask*
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THEN DEST[i+15:i] := TruncateQuadWordToWord (SRC[m+63:m])
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ELSE
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IF *merging-masking* ; merging-masking
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THEN *DEST[i+15:i] remains unchanged*
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ELSE *zeroing-masking*
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; zeroing-masking
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DEST[i+15:i] := 0
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FI
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FI;
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ENDFOR
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DEST[MAXVL-1:VL/4] := 0;
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</pre>
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<h4 id="vpmovqw-instruction--evex-encoded-versions--when-dest-is-memory">VPMOVQW instruction (EVEX encoded versions) when dest is memory<a class="anchor" href="#vpmovqw-instruction--evex-encoded-versions--when-dest-is-memory">
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¶
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</a></h4>
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<pre>(KL, VL) = (2, 128), (4, 256), (8, 512)
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FOR j := 0 TO KL-1
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i := j * 16
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m := j * 64
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IF k1[j] OR *no writemask*
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THEN DEST[i+15:i] := TruncateQuadWordToWord (SRC[m+63:m])
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ELSE
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*DEST[i+15:i] remains unchanged* ; merging-masking
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FI;
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ENDFOR
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</pre>
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<h4 id="vpmovsqw-instruction--evex-encoded-versions--when-dest-is-a-register">VPMOVSQW instruction (EVEX encoded versions) when dest is a register<a class="anchor" href="#vpmovsqw-instruction--evex-encoded-versions--when-dest-is-a-register">
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¶
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</a></h4>
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<pre>(KL, VL) = (2, 128), (4, 256), (8, 512)
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FOR j := 0 TO KL-1
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i := j * 16
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m := j * 64
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IF k1[j] OR *no writemask*
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THEN DEST[i+15:i] := SaturateSignedQuadWordToWord (SRC[m+63:m])
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ELSE
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IF *merging-masking* ; merging-masking
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THEN *DEST[i+15:i] remains unchanged*
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ELSE *zeroing-masking*
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; zeroing-masking
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DEST[i+15:i] := 0
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FI
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FI;
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ENDFOR
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DEST[MAXVL-1:VL/4] := 0;
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</pre>
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<h4 id="vpmovsqw-instruction--evex-encoded-versions--when-dest-is-memory">VPMOVSQW instruction (EVEX encoded versions) when dest is memory<a class="anchor" href="#vpmovsqw-instruction--evex-encoded-versions--when-dest-is-memory">
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¶
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</a></h4>
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<pre>(KL, VL) = (2, 128), (4, 256), (8, 512)
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FOR j := 0 TO KL-1
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i := j * 16
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m := j * 64
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IF k1[j] OR *no writemask*
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THEN DEST[i+15:i] := SaturateSignedQuadWordToWord (SRC[m+63:m])
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ELSE
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*DEST[i+15:i] remains unchanged* ; merging-masking
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FI;
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ENDFOR
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</pre>
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<h4 id="vpmovusqw-instruction--evex-encoded-versions--when-dest-is-a-register">VPMOVUSQW instruction (EVEX encoded versions) when dest is a register<a class="anchor" href="#vpmovusqw-instruction--evex-encoded-versions--when-dest-is-a-register">
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¶
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</a></h4>
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<pre>(KL, VL) = (2, 128), (4, 256), (8, 512)
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FOR j := 0 TO KL-1
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i := j * 16
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m := j * 64
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IF k1[j] OR *no writemask*
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THEN DEST[i+15:i] := SaturateUnsignedQuadWordToWord (SRC[m+63:m])
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ELSE
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IF *merging-masking* ; merging-masking
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THEN *DEST[i+15:i] remains unchanged*
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ELSE *zeroing-masking*
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; zeroing-masking
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DEST[i+15:i] := 0
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FI
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FI;
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ENDFOR
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DEST[MAXVL-1:VL/4] := 0;
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</pre>
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<h4 id="vpmovusqw-instruction--evex-encoded-versions--when-dest-is-memory">VPMOVUSQW instruction (EVEX encoded versions) when dest is memory<a class="anchor" href="#vpmovusqw-instruction--evex-encoded-versions--when-dest-is-memory">
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¶
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</a></h4>
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<pre>(KL, VL) = (2, 128), (4, 256), (8, 512)
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FOR j := 0 TO KL-1
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i := j * 16
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m := j * 64
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IF k1[j] OR *no writemask*
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THEN DEST[i+15:i] := SaturateUnsignedQuadWordToWord (SRC[m+63:m])
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ELSE
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*DEST[i+15:i] remains unchanged* ; merging-masking
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FI;
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ENDFOR
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</pre>
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<h3 id="intel-c-c++-compiler-intrinsic-equivalents">Intel C/C++ Compiler Intrinsic Equivalents<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalents">
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¶
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</a></h3>
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<pre>VPMOVQW __m128i _mm512_cvtepi64_epi16( __m512i a);
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</pre>
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<pre>VPMOVQW __m128i _mm512_mask_cvtepi64_epi16(__m128i s, __mmask8 k, __m512i a);
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</pre>
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<pre>VPMOVQW __m128i _mm512_maskz_cvtepi64_epi16( __mmask8 k, __m512i a);
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</pre>
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<pre>VPMOVQW void _mm512_mask_cvtepi64_storeu_epi16(void * d, __mmask8 k, __m512i a);
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</pre>
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<pre>VPMOVSQW __m128i _mm512_cvtsepi64_epi16( __m512i a);
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</pre>
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<pre>VPMOVSQW __m128i _mm512_mask_cvtsepi64_epi16(__m128i s, __mmask8 k, __m512i a);
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</pre>
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<pre>VPMOVSQW __m128i _mm512_maskz_cvtsepi64_epi16( __mmask8 k, __m512i a);
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</pre>
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<pre>VPMOVSQW void _mm512_mask_cvtsepi64_storeu_epi16(void * d, __mmask8 k, __m512i a);
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</pre>
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<pre>VPMOVUSQW __m128i _mm512_cvtusepi64_epi16( __m512i a);
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</pre>
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<pre>VPMOVUSQW __m128i _mm512_mask_cvtusepi64_epi16(__m128i s, __mmask8 k, __m512i a);
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</pre>
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<pre>VPMOVUSQW __m128i _mm512_maskz_cvtusepi64_epi16( __mmask8 k, __m512i a);
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</pre>
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<pre>VPMOVUSQW void _mm512_mask_cvtusepi64_storeu_epi16(void * d, __mmask8 k, __m512i a);
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</pre>
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<pre>VPMOVUSQD __m128i _mm256_cvtusepi64_epi32(__m256i a);
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</pre>
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<pre>VPMOVUSQD __m128i _mm256_mask_cvtusepi64_epi32(__m128i a, __mmask8 k, __m256i b);
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</pre>
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<pre>VPMOVUSQD __m128i _mm256_maskz_cvtusepi64_epi32( __mmask8 k, __m256i b);
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</pre>
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<pre>VPMOVUSQD void _mm256_mask_cvtusepi64_storeu_epi32(void * , __mmask8 k, __m256i b);
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</pre>
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<pre>VPMOVUSQD __m128i _mm_cvtusepi64_epi32(__m128i a);
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</pre>
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<pre>VPMOVUSQD __m128i _mm_mask_cvtusepi64_epi32(__m128i a, __mmask8 k, __m128i b);
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</pre>
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<pre>VPMOVUSQD __m128i _mm_maskz_cvtusepi64_epi32( __mmask8 k, __m128i b);
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</pre>
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<pre>VPMOVUSQD void _mm_mask_cvtusepi64_storeu_epi32(void * , __mmask8 k, __m128i b);
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</pre>
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<pre>VPMOVSQD __m128i _mm256_cvtsepi64_epi32(__m256i a);
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</pre>
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<pre>VPMOVSQD __m128i _mm256_mask_cvtsepi64_epi32(__m128i a, __mmask8 k, __m256i b);
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</pre>
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<pre>VPMOVSQD __m128i _mm256_maskz_cvtsepi64_epi32( __mmask8 k, __m256i b);
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</pre>
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<pre>VPMOVSQD void _mm256_mask_cvtsepi64_storeu_epi32(void * , __mmask8 k, __m256i b);
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</pre>
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<pre>VPMOVSQD __m128i _mm_cvtsepi64_epi32(__m128i a);
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</pre>
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<pre>VPMOVSQD __m128i _mm_mask_cvtsepi64_epi32(__m128i a, __mmask8 k, __m128i b);
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</pre>
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<pre>VPMOVSQD __m128i _mm_maskz_cvtsepi64_epi32( __mmask8 k, __m128i b);
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</pre>
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<pre>VPMOVSQD void _mm_mask_cvtsepi64_storeu_epi32(void * , __mmask8 k, __m128i b);
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</pre>
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<pre>VPMOVQD __m128i _mm256_cvtepi64_epi32(__m256i a);
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</pre>
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<pre>VPMOVQD __m128i _mm256_mask_cvtepi64_epi32(__m128i a, __mmask8 k, __m256i b);
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</pre>
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<pre>VPMOVQD __m128i _mm256_maskz_cvtepi64_epi32( __mmask8 k, __m256i b);
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</pre>
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<pre>VPMOVQD void _mm256_mask_cvtepi64_storeu_epi32(void * , __mmask8 k, __m256i b);
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</pre>
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<pre>VPMOVQD __m128i _mm_cvtepi64_epi32(__m128i a);
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</pre>
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<pre>VPMOVQD __m128i _mm_mask_cvtepi64_epi32(__m128i a, __mmask8 k, __m128i b);
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</pre>
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<pre>VPMOVQD __m128i _mm_maskz_cvtepi64_epi32( __mmask8 k, __m128i b);
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</pre>
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<pre>VPMOVQD void _mm_mask_cvtepi64_storeu_epi32(void * , __mmask8 k, __m128i b);
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</pre>
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<h3 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h3>
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<p>None.</p>
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<h3 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h3>
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<p>EVEX-encoded instruction, see <span class="not-imported">Table 2-53</span>, “Type E6 Class Exception Conditions.”</p>
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<p>Additionally:</p>
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<table>
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<tr>
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<td>#UD</td>
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<td>If EVEX.vvvv != 1111B.</td></tr></table><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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