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<!DOCTYPE html>
<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>VMOVSH
— Move Scalar FP16 Value</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>VMOVSH
— Move Scalar FP16 Value</h1>
<table>
<tr>
<th> Instruction En bit Mode Flag
Support Instruction En bit Mode Flag
Support 64/32 CPUID Feature Instruction En bit Mode Flag CPUID Feature Instruction En bit Mode Flag Op/ 64/32 CPUID Feature Instruction En bit Mode Flag 64/32 CPUID Feature Instruction En bit Mode Flag CPUID Feature Instruction En bit Mode Flag Op/ 64/32 CPUID Feature </th>
<th></th>
<th>Support</th>
<th></th>
<th>Description</th></tr>
<tr>
<td>EVEX.LLIG.F3.MAP5.W0 10 /r VMOVSH xmm1{k1}{z}, m16</td>
<td>A</td>
<td>V/V</td>
<td>AVX512-FP16</td>
<td>Move FP16 value from m16 to xmm1 subject to writemask k1.</td></tr>
<tr>
<td>EVEX.LLIG.F3.MAP5.W0 11 /r VMOVSH m16{k1}, xmm1</td>
<td>B</td>
<td>V/V</td>
<td>AVX512-FP16</td>
<td>Move low FP16 value from xmm1 to m16 subject to writemask k1.</td></tr>
<tr>
<td>EVEX.LLIG.F3.MAP5.W0 10 /r VMOVSH xmm1{k1}{z}, xmm2, xmm3</td>
<td>C</td>
<td>V/V</td>
<td>AVX512-FP16</td>
<td>Move low FP16 values from xmm3 to xmm1 subject to writemask k1. Bits 127:16 of xmm2 are copied to xmm1[127:16].</td></tr>
<tr>
<td>EVEX.LLIG.F3.MAP5.W0 11 /r VMOVSH xmm1{k1}{z}, xmm2, xmm3</td>
<td>D</td>
<td>V/V</td>
<td>AVX512-FP16</td>
<td>Move low FP16 values from xmm3 to xmm1 subject to writemask k1. Bits 127:16 of xmm2 are copied to xmm1[127:16].</td></tr></table>
<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
</a></h2>
<table>
<tr>
<th>Op/En</th>
<th>Tuple</th>
<th>Operand 1</th>
<th>Operand 2</th>
<th>Operand 3</th>
<th>Operand 4</th></tr>
<tr>
<td>A</td>
<td>Scalar</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>N/A</td>
<td>N/A</td></tr>
<tr>
<td>B</td>
<td>Scalar</td>
<td>ModRM:r/m (w)</td>
<td>ModRM:reg (r)</td>
<td>N/A</td>
<td>N/A</td></tr>
<tr>
<td>C</td>
<td>N/A</td>
<td>ModRM:reg (w)</td>
<td>VEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>N/A</td></tr>
<tr>
<td>D</td>
<td>N/A</td>
<td>ModRM:r/m (w)</td>
<td>VEX.vvvv (r)</td>
<td>ModRM:reg (r)</td>
<td>N/A</td></tr></table>
<h3 id="description">Description<a class="anchor" href="#description">
</a></h3>
<p>This instruction moves a FP16 value to a register or memory location.</p>
<p>The two register-only forms are aliases and differ only in where their operands are encoded; this is a side effect of the encodings selected.</p>
<h3 id="operation">Operation<a class="anchor" href="#operation">
</a></h3>
<h4 id="vmovsh-dest--src--two-operand-load-">VMOVSH dest, src (two operand load)<a class="anchor" href="#vmovsh-dest--src--two-operand-load-">
</a></h4>
<pre>IF k1[0] or no writemask:
DEST.fp16[0] := SRC.fp16[0]
ELSE IF *zeroing*:
DEST.fp16[0] := 0
// ELSE DEST.fp16[0] remains unchanged
DEST[MAXVL:16] := 0
</pre>
<h4 id="vmovsh-dest--src--two-operand-store-">VMOVSH dest, src (two operand store)<a class="anchor" href="#vmovsh-dest--src--two-operand-store-">
</a></h4>
<pre>IF k1[0] or no writemask:
DEST.fp16[0] := SRC.fp16[0]
// ELSE DEST.fp16[0] remains unchanged
</pre>
<h4 id="vmovsh-dest--src1--src2--three-operand-copy-">VMOVSH dest, src1, src2 (three operand copy)<a class="anchor" href="#vmovsh-dest--src1--src2--three-operand-copy-">
</a></h4>
<pre>IF k1[0] or no writemask:
DEST.fp16[0] := SRC2.fp16[0]
ELSE IF *zeroing*:
DEST.fp16[0] := 0
// ELSE DEST.fp16[0] remains unchanged
DEST[127:16] := SRC1[127:16]
DEST[MAXVL:128] := 0
</pre>
<h3 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
</a></h3>
<pre>VMOVSH __m128h _mm_load_sh (void const* mem_addr);
</pre>
<pre>VMOVSH __m128h _mm_mask_load_sh (__m128h src, __mmask8 k, void const* mem_addr);
</pre>
<pre>VMOVSH __m128h _mm_maskz_load_sh (__mmask8 k, void const* mem_addr);
</pre>
<pre>VMOVSH __m128h _mm_mask_move_sh (__m128h src, __mmask8 k, __m128h a, __m128h b);
</pre>
<pre>VMOVSH __m128h _mm_maskz_move_sh (__mmask8 k, __m128h a, __m128h b);
</pre>
<pre>VMOVSH __m128h _mm_move_sh (__m128h a, __m128h b);
</pre>
<pre>VMOVSH void _mm_mask_store_sh (void * mem_addr, __mmask8 k, __m128h a);
</pre>
<pre>VMOVSH void _mm_store_sh (void * mem_addr, __m128h a);
</pre>
<h3 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
</a></h3>
<p>None</p>
<h3 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
</a></h3>
<p>EVEX-encoded instruction, see <span class="not-imported">Table 2-51</span>, “Type E5 Class Exception Conditions.”</p><footer><p>
This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
</p></footer></body></html>
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