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HTML
147 lines
6.6 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>VERR/VERW
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— Verify a Segment for Reading or Writing</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>VERR/VERW
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— Verify a Segment for Reading or Writing</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64-Bit Mode</th>
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<th>Compat/Leg Mode</th>
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<th>Description</th></tr>
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<tr>
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<td>0F 00 /4 VERR r/m16</td>
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<td>M</td>
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<td>Valid</td>
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<td>Valid</td>
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<td>Set ZF=1 if segment specified with r/m16 can be read.</td></tr>
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<tr>
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<td>0F 00 /5 VERW r/m16</td>
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<td>M</td>
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<td>Valid</td>
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<td>Valid</td>
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<td>Set ZF=1 if segment specified with r/m16 can be written.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>M</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Verifies whether the code or data segment specified with the source operand is readable (VERR) or writable (VERW) from the current privilege level (CPL). The source operand is a 16-bit register or a memory location that contains the segment selector for the segment to be verified. If the segment is accessible and readable (VERR) or writable (VERW), the ZF flag is set; otherwise, the ZF flag is cleared. Code segments are never verified as writable. This check cannot be performed on system segments.</p>
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<p>To set the ZF flag, the following conditions must be met:</p>
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<ul>
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<li>The segment selector is not NULL.</li>
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<li>The selector must denote a descriptor within the bounds of the descriptor table (GDT or LDT).</li>
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<li>The selector must denote the descriptor of a code or data segment (not that of a system segment or gate).</li>
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<li>For the VERR instruction, the segment must be readable.</li>
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<li>For the VERW instruction, the segment must be a writable data segment.</li>
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<li>If the segment is not a conforming code segment, the segment’s DPL must be greater than or equal to (have less or the same privilege as) both the CPL and the segment selector's RPL.</li></ul>
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<p>The validation performed is the same as is performed when a segment selector is loaded into the DS, ES, FS, or GS register, and the indicated access (read or write) is performed. The segment selector's value cannot result in a protection exception, enabling the software to anticipate possible segment access problems.</p>
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<p>This instruction’s operation is the same in non-64-bit modes and 64-bit mode. The operand size is fixed at 16 bits.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<pre>IF SRC(Offset) > (GDTR(Limit) or (LDTR(Limit))
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THEN ZF := 0; FI;
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Read segment descriptor;
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IF SegmentDescriptor(DescriptorType) = 0 (* System segment *)
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or (SegmentDescriptor(Type) ≠ conforming code segment)
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and (CPL > DPL) or (RPL > DPL)
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THEN
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ZF := 0;
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ELSE
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IF ((Instruction = VERR) and (Segment readable))
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or ((Instruction = VERW) and (Segment writable))
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THEN
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ZF := 1;
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ELSE
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ZF := 0;
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FI;
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FI;
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</pre>
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<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
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¶
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</a></h2>
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<p>The ZF flag is set to 1 if the segment is accessible and readable (VERR) or writable (VERW); otherwise, it is set to 0.</p>
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<h2 class="exceptions" id="protected-mode-exceptions">Protected Mode Exceptions<a class="anchor" href="#protected-mode-exceptions">
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¶
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</a></h2>
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<p>The only exceptions generated for these instructions are those related to illegal addressing of the source operand.</p>
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<table>
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<tr>
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<td rowspan="2">#GP(0)</td>
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<td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
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<tr>
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<td>If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector.</td></tr>
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<tr>
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<td>#SS(0)</td>
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<td>If a memory operand effective address is outside the SS segment limit.</td></tr>
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<tr>
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<td>#PF(fault-code)</td>
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<td>If a page fault occurs.</td></tr>
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<tr>
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<td>#AC(0)</td>
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<td>If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.</td></tr>
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<tr>
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<td>#UD</td>
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<td>If the LOCK prefix is used.</td></tr></table>
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<h2 class="exceptions" id="real-address-mode-exceptions">Real-Address Mode Exceptions<a class="anchor" href="#real-address-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td rowspan="2">#UD</td>
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<td>The VERR and VERW instructions are not recognized in real-address mode.</td></tr>
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<tr>
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<td>If the LOCK prefix is used.</td></tr></table>
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<h2 class="exceptions" id="virtual-8086-mode-exceptions">Virtual-8086 Mode Exceptions<a class="anchor" href="#virtual-8086-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td rowspan="2">#UD</td>
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<td>The VERR and VERW instructions are not recognized in virtual-8086 mode.</td></tr>
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<tr>
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<td>If the LOCK prefix is used.</td></tr></table>
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<h2 class="exceptions" id="compatibility-mode-exceptions">Compatibility Mode Exceptions<a class="anchor" href="#compatibility-mode-exceptions">
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¶
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</a></h2>
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<p>Same exceptions as in protected mode.</p>
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<h2 class="exceptions" id="64-bit-mode-exceptions">64-Bit Mode Exceptions<a class="anchor" href="#64-bit-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td>#SS(0)</td>
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<td>If a memory address referencing the SS segment is in a non-canonical form.</td></tr>
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<tr>
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<td>#GP(0)</td>
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<td>If the memory address is in a non-canonical form.</td></tr>
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<tr>
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<td>#PF(fault-code)</td>
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<td>If a page fault occurs.</td></tr>
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<tr>
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<td>#AC(0)</td>
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<td>If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.</td></tr>
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<tr>
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<td>#UD</td>
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<td>If the LOCK prefix is used.</td></tr></table><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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