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152 lines
6.6 KiB
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>VCVTUDQ2PS
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— Convert Packed Unsigned Doubleword Integers to Packed Single PrecisionFloating-Point Values</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>VCVTUDQ2PS
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— Convert Packed Unsigned Doubleword Integers to Packed Single PrecisionFloating-Point Values</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32 Bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>EVEX.128.F2.0F.W0 7A /r VCVTUDQ2PS xmm1 {k1}{z}, xmm2/m128/m32bcst</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512VL AVX512F</td>
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<td>Convert four packed unsigned doubleword integers from xmm2/m128/m32bcst to packed single precision floating-point values in xmm1 with writemask k1.</td></tr>
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<tr>
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<td>EVEX.256.F2.0F.W0 7A /r VCVTUDQ2PS ymm1 {k1}{z}, ymm2/m256/m32bcst</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512VL AVX512F</td>
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<td>Convert eight packed unsigned doubleword integers from ymm2/m256/m32bcst to packed single precision floating-point values in zmm1 with writemask k1.</td></tr>
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<tr>
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<td>EVEX.512.F2.0F.W0 7A /r VCVTUDQ2PS zmm1 {k1}{z}, zmm2/m512/m32bcst{er}</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512F</td>
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<td>Convert sixteen packed unsigned doubleword integers from zmm2/m512/m32bcst to sixteen packed single precision floating-point values in zmm1 with writemask k1.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple Type</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>Full</td>
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<td>ModRM:reg (w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h3 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h3>
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<p>Converts packed unsigned doubleword integers in the source operand (second operand) to single precision floating-point values in the destination operand (first operand).</p>
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<p>The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1.</p>
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<p>Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.</p>
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<h3 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h3>
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<h4 id="vcvtudq2ps--evex-encoded-version--when-src-operand-is-a-register">VCVTUDQ2PS (EVEX Encoded Version) When SRC Operand is a Register<a class="anchor" href="#vcvtudq2ps--evex-encoded-version--when-src-operand-is-a-register">
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¶
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</a></h4>
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<pre>(KL, VL) = (4, 128), (8, 256), (16, 512)
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IF (VL = 512) AND (EVEX.b = 1)
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THEN
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SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);
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ELSE
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SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);
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FI;
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FOR j := 0 TO KL-1
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i := j * 32
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IF k1[j] OR *no writemask*
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THEN DEST[i+31:i] :=
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Convert_UInteger_To_Single_Precision_Floating_Point(SRC[i+31:i])
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ELSE
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IF *merging-masking* ; merging-masking
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THEN *DEST[i+31:i] remains unchanged*
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ELSE ; zeroing-masking
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DEST[i+31:i] := 0
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FI
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FI;
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ENDFOR
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DEST[MAXVL-1:VL] := 0
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</pre>
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<h4 id="vcvtudq2ps--evex-encoded-version--when-src-operand-is-a-memory-source">VCVTUDQ2PS (EVEX Encoded Version) When SRC Operand is a Memory Source<a class="anchor" href="#vcvtudq2ps--evex-encoded-version--when-src-operand-is-a-memory-source">
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¶
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</a></h4>
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<pre>(KL, VL) = (4, 128), (8, 256), (16, 512)
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FOR j := 0 TO KL-1
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i := j * 32
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IF k1[j] OR *no writemask*
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THEN
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IF (EVEX.b = 1)
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THEN
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DEST[i+31:i] :=
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Convert_UInteger_To_Single_Precision_Floating_Point(SRC[31:0])
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ELSE
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DEST[i+31:i] :=
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Convert_UInteger_To_Single_Precision_Floating_Point(SRC[i+31:i])
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FI;
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ELSE
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IF *merging-masking* ; merging-masking
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THEN *DEST[i+31:i] remains unchanged*
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ELSE ; zeroing-masking
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DEST[i+31:i] := 0
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FI
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FI;
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ENDFOR
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DEST[MAXVL-1:VL] := 0
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</pre>
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<h3 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h3>
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<pre>VCVTUDQ2PS __m512 _mm512_cvtepu32_ps( __m512i a);
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</pre>
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<pre>VCVTUDQ2PS __m512 _mm512_mask_cvtepu32_ps( __m512 s, __mmask16 k, __m512i a);
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</pre>
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<pre>VCVTUDQ2PS __m512 _mm512_maskz_cvtepu32_ps( __mmask16 k, __m512i a);
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</pre>
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<pre>VCVTUDQ2PS __m512 _mm512_cvt_roundepu32_ps( __m512i a, int r);
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</pre>
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<pre>VCVTUDQ2PS __m512 _mm512_mask_cvt_roundepu32_ps( __m512 s, __mmask16 k, __m512i a, int r);
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</pre>
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<pre>VCVTUDQ2PS __m512 _mm512_maskz_cvt_roundepu32_ps( __mmask16 k, __m512i a, int r);
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</pre>
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<pre>VCVTUDQ2PS __m256 _mm256_cvtepu32_ps( __m256i a);
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</pre>
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<pre>VCVTUDQ2PS __m256 _mm256_mask_cvtepu32_ps( __m256 s, __mmask8 k, __m256i a);
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</pre>
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<pre>VCVTUDQ2PS __m256 _mm256_maskz_cvtepu32_ps( __mmask8 k, __m256i a);
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</pre>
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<pre>VCVTUDQ2PS __m128 _mm_cvtepu32_ps( __m128i a);
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</pre>
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<pre>VCVTUDQ2PS __m128 _mm_mask_cvtepu32_ps( __m128 s, __mmask8 k, __m128i a);
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</pre>
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<pre>VCVTUDQ2PS __m128 _mm_maskz_cvtepu32_ps( __mmask8 k, __m128i a);
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</pre>
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<h3 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h3>
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<p>Precision.</p>
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<h3 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h3>
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<p>EVEX-encoded instructions, see <span class="not-imported">Table 2-46</span>, “Type E2 Class Exception Conditions.”</p>
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<p>Additionally:</p>
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<table>
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<tr>
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<td>#UD</td>
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<td>If EVEX.vvvv != 1111B.</td></tr></table><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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