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132 lines
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HTML
132 lines
6.5 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>PINSRW
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— Insert Word</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>PINSRW
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— Insert Word</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/ En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>NP 0F C4 /<em>r</em> ib<sup>1</sup> PINSRW mm, r32/m16, imm8</td>
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<td>A</td>
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<td>V/V</td>
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<td>SSE</td>
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<td>Insert the low word from r32 or from m16 into mm at the word position specified by imm8.</td></tr>
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<tr>
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<td>66 0F C4 /<em>r</em> ib PINSRW xmm, r32/m16, imm8</td>
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<td>A</td>
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<td>V/V</td>
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<td>SSE2</td>
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<td>Move the low word of r32 or from m16 into xmm at the word position specified by imm8.</td></tr>
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<tr>
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<td>VEX.128.66.0F.W0 C4 /r ib VPINSRW xmm1, xmm2, r32/m16, imm8</td>
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<td>B</td>
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<td>V<sup>2</sup>/V</td>
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<td>AVX</td>
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<td>Insert the word from r32/m16 at the offset indicated by imm8 into the value from xmm2 and store result in xmm1.</td></tr>
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<tr>
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<td>EVEX.128.66.0F.WIG C4 /r ib VPINSRW xmm1, xmm2, r32/m16, imm8</td>
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<td>C</td>
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<td>V/V</td>
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<td>AVX512BW</td>
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<td>Insert the word from r32/m16 at the offset indicated by imm8 into the value from xmm2 and store result in xmm1.</td></tr></table>
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<blockquote>
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<p>1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Classification,” in the Intel<sup>®</sup> 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A, and Section 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers,” in the Intel<sup>®</sup> 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.</p>
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<p>2. In 64-bit mode, VEX.W1 is ignored for VPINSRW (similar to legacy REX.W=1 prefix in PINSRW).</p></blockquote>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple Type</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>N/A</td>
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<td>ModRM:reg (w)</td>
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<td>ModRM:r/m (r)</td>
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<td>imm8</td>
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<td>N/A</td></tr>
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<tr>
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<td>B</td>
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<td>N/A</td>
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<td>ModRM:reg (w)</td>
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<td>VEX.vvvv (r)</td>
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<td>ModRM:r/m (r)</td>
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<td>imm8</td></tr>
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<tr>
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<td>C</td>
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<td>Tuple1 Scalar</td>
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<td>ModRM:reg (w)</td>
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<td>EVEX.vvvv (r)</td>
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<td>ModRM:r/m (r)</td>
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<td>imm8</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Three operand MMX and SSE instructions:</p>
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<p>Copies a word from the source operand and inserts it in the destination operand at the location specified with the count operand. (The other words in the destination register are left untouched.) The source operand can be a general-purpose register or a 16-bit memory location. (When the source operand is a general-purpose register, the low word of the register is copied.) The destination operand can be an MMX technology register or an XMM register. The count operand is an 8-bit immediate. When specifying a word location in an MMX technology register, the 2 least-significant bits of the count operand specify the location; for an XMM register, the 3 least-significant bits specify the location.</p>
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<p>Bits (MAXVL-1:128) of the corresponding YMM destination register remain unchanged.</p>
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<p>Four operand AVX and AVX-512 instructions:</p>
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<p>Combines a word from the first source operand with the second source operand, and inserts it in the destination operand at the location specified with the count operand. The second source operand can be a general-purpose register or a 16-bit memory location. (When the source operand is a general-purpose register, the low word of the register is copied.) The first source and destination operands are XMM registers. The count operand is an 8-bit immediate. When specifying a word location, the 3 least-significant bits specify the location.</p>
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<p>Bits (MAXVL-1:128) of the destination YMM register are zeroed. VEX.L/EVEX.L’L must be 0, otherwise the instruction will #UD.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<h3 id="pinsrw-dest--src--imm8--mmx-">PINSRW dest, src, imm8 (MMX)<a class="anchor" href="#pinsrw-dest--src--imm8--mmx-">
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¶
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</a></h3>
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<pre>SEL := imm8[1:0]
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DEST.word[SEL] := src.word[0]
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</pre>
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<h3 id="pinsrw-dest--src--imm8--sse-">PINSRW dest, src, imm8 (SSE)<a class="anchor" href="#pinsrw-dest--src--imm8--sse-">
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¶
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</a></h3>
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<pre>SEL := imm8[2:0]
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DEST.word[SEL] := src.word[0]
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</pre>
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<h3 id="vpinsrw-dest--src1--src2--imm8--avx-avx512-">VPINSRW dest, src1, src2, imm8 (AVX/AVX512)<a class="anchor" href="#vpinsrw-dest--src1--src2--imm8--avx-avx512-">
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¶
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</a></h3>
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<pre>SEL := imm8[2:0]
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DEST := src1
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DEST.word[SEL] := src2.word[0]
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DEST[MAXVL-1:128] := 0
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</pre>
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<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h2>
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<pre>PINSRW __m64 _mm_insert_pi16 (__m64 a, int d, int n)
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</pre>
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<pre>PINSRW __m128i _mm_insert_epi16 ( __m128i a, int b, int imm)
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</pre>
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<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="numeric-exceptions">Numeric Exceptions<a class="anchor" href="#numeric-exceptions">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h2>
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<p>EVEX-encoded instruction, see <span class="not-imported">Table 2-22</span>, “Type 5 Class Exception Conditions.”</p>
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<p>EVEX-encoded instruction, see <span class="not-imported">Table 2-57</span>, “Type E9NF Class Exception Conditions.”</p>
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<p>Additionally:</p>
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<table>
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<tr>
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<td>#UD</td>
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<td>If VEX.L = 1 or EVEX.L’L > 0.</td></tr></table><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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