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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>PHADDSW
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— Packed Horizontal Add and Saturate</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>PHADDSW
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— Packed Horizontal Add and Saturate</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>NP 0F 38 03 /r<sup>1</sup> PHADDSW mm1, mm2/m64</td>
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<td>RM</td>
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<td>V/V</td>
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<td>SSSE3</td>
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<td>Add 16-bit signed integers horizontally, pack saturated integers to mm1.</td></tr>
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<tr>
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<td>66 0F 38 03 /r PHADDSW xmm1, xmm2/m128</td>
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<td>RM</td>
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<td>V/V</td>
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<td>SSSE3</td>
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<td>Add 16-bit signed integers horizontally, pack saturated integers to xmm1.</td></tr>
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<tr>
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<td>VEX.128.66.0F38.WIG 03 /r VPHADDSW xmm1, xmm2, xmm3/m128</td>
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<td>RVM</td>
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<td>V/V</td>
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<td>AVX</td>
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<td>Add 16-bit signed integers horizontally, pack saturated integers to xmm1.</td></tr>
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<tr>
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<td>VEX.256.66.0F38.WIG 03 /r VPHADDSW ymm1, ymm2, ymm3/m256</td>
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<td>RVM</td>
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<td>V/V</td>
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<td>AVX2</td>
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<td>Add 16-bit signed integers horizontally, pack saturated integers to ymm1.</td></tr></table>
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<blockquote>
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<p>1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Classification,” in the Intel<sup>®</sup> 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A, and Section 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers,” in the Intel<sup>®</sup> 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.</p></blockquote>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>RM</td>
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<td>ModRM:reg (r, w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr>
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<tr>
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<td>RVM</td>
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<td>ModRM:reg (w)</td>
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<td>VEX.vvvv (r)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>(V)PHADDSW adds two adjacent signed 16-bit integers horizontally from the source and destination operands and saturates the signed results; packs the signed, saturated 16-bit results to the destination operand (first operand) When the source operand is a 128-bit memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated.</p>
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<p>Legacy SSE version: Both operands can be MMX registers. The second source operand can be an MMX register or a 64-bit memory location.</p>
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<p>128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding YMM destination register remain unchanged.</p>
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<p>In 64-bit mode, use the REX prefix to access additional registers.</p>
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<p>VEX.128 encoded version: The first source and destination operands are XMM registers. The second source operand is an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the destination YMM register are zeroed.</p>
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<p>VEX.256 encoded version: The first source and destination operands are YMM registers. The second source operand can be an YMM register or a 256-bit memory location.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<h3 id="phaddsw--with-64-bit-operands-">PHADDSW (With 64-bit Operands)<a class="anchor" href="#phaddsw--with-64-bit-operands-">
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¶
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</a></h3>
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<pre>mm1[15-0] = SaturateToSignedWord((mm1[31-16] + mm1[15-0]);
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mm1[31-16] = SaturateToSignedWord(mm1[63-48] + mm1[47-32]);
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mm1[47-32] = SaturateToSignedWord(mm2/m64[31-16] + mm2/m64[15-0]);
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mm1[63-48] = SaturateToSignedWord(mm2/m64[63-48] + mm2/m64[47-32]);
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</pre>
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<h3 id="phaddsw--with-128-bit-operands-">PHADDSW (With 128-bit Operands)<a class="anchor" href="#phaddsw--with-128-bit-operands-">
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¶
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</a></h3>
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<pre>xmm1[15-0]= SaturateToSignedWord(xmm1[31-16] + xmm1[15-0]);
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xmm1[31-16] = SaturateToSignedWord(xmm1[63-48] + xmm1[47-32]);
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xmm1[47-32] = SaturateToSignedWord(xmm1[95-80] + xmm1[79-64]);
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xmm1[63-48] = SaturateToSignedWord(xmm1[127-112] + xmm1[111-96]);
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xmm1[79-64] = SaturateToSignedWord(xmm2/m128[31-16] + xmm2/m128[15-0]);
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xmm1[95-80] = SaturateToSignedWord(xmm2/m128[63-48] + xmm2/m128[47-32]);
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xmm1[111-96] = SaturateToSignedWord(xmm2/m128[95-80] + xmm2/m128[79-64]);
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xmm1[127-112] = SaturateToSignedWord(xmm2/m128[127-112] + xmm2/m128[111-96]);
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</pre>
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<h3 id="vphaddsw--vex-128-encoded-version-">VPHADDSW (VEX.128 Encoded Version)<a class="anchor" href="#vphaddsw--vex-128-encoded-version-">
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¶
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</a></h3>
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<pre>DEST[15:0]= SaturateToSignedWord(SRC1[31:16] + SRC1[15:0])
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DEST[31:16] = SaturateToSignedWord(SRC1[63:48] + SRC1[47:32])
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DEST[47:32] = SaturateToSignedWord(SRC1[95:80] + SRC1[79:64])
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DEST[63:48] = SaturateToSignedWord(SRC1[127:112] + SRC1[111:96])
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DEST[79:64] = SaturateToSignedWord(SRC2[31:16] + SRC2[15:0])
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DEST[95:80] = SaturateToSignedWord(SRC2[63:48] + SRC2[47:32])
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DEST[111:96] = SaturateToSignedWord(SRC2[95:80] + SRC2[79:64])
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DEST[127:112] = SaturateToSignedWord(SRC2[127:112] + SRC2[111:96])
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DEST[MAXVL-1:128] := 0
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</pre>
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<h3 id="vphaddsw--vex-256-encoded-version-">VPHADDSW (VEX.256 Encoded Version)<a class="anchor" href="#vphaddsw--vex-256-encoded-version-">
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¶
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</a></h3>
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<pre>DEST[15:0]= SaturateToSignedWord(SRC1[31:16] + SRC1[15:0])
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DEST[31:16] = SaturateToSignedWord(SRC1[63:48] + SRC1[47:32])
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DEST[47:32] = SaturateToSignedWord(SRC1[95:80] + SRC1[79:64])
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DEST[63:48] = SaturateToSignedWord(SRC1[127:112] + SRC1[111:96])
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DEST[79:64] = SaturateToSignedWord(SRC2[31:16] + SRC2[15:0])
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DEST[95:80] = SaturateToSignedWord(SRC2[63:48] + SRC2[47:32])
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DEST[111:96] = SaturateToSignedWord(SRC2[95:80] + SRC2[79:64])
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DEST[127:112] = SaturateToSignedWord(SRC2[127:112] + SRC2[111:96])
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DEST[143:128]= SaturateToSignedWord(SRC1[159:144] + SRC1[143:128])
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DEST[159:144] = SaturateToSignedWord(SRC1[191:176] + SRC1[175:160])
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DEST[175:160] = SaturateToSignedWord( SRC1[223:208] + SRC1[207:192])
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DEST[191:176] = SaturateToSignedWord(SRC1[255:240] + SRC1[239:224])
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DEST[207:192] = SaturateToSignedWord(SRC2[127:112] + SRC2[143:128])
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DEST[223:208] = SaturateToSignedWord(SRC2[159:144] + SRC2[175:160])
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DEST[239:224] = SaturateToSignedWord(SRC2[191-160] + SRC2[159-128])
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DEST[255:240] = SaturateToSignedWord(SRC2[255:240] + SRC2[239:224])
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</pre>
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<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h2>
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<pre>PHADDSW __m64 _mm_hadds_pi16 (__m64 a, __m64 b)
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</pre>
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<pre>(V)PHADDSW __m128i _mm_hadds_epi16 (__m128i a, __m128i b)
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</pre>
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<pre>VPHADDSW __m256i _mm256_hadds_epi16 (__m256i a, __m256i b)
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</pre>
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<h2 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h2>
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<p>See <span class="not-imported">Table 2-21</span>, “Type 4 Class Exception Conditions,” additionally:</p>
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<table>
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<tr>
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<td>#UD</td>
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<td>If VEX.L = 1.</td></tr></table><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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