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<!DOCTYPE html>
<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>HSUBPD
— Packed Double Precision Floating-Point Horizontal Subtract</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>HSUBPD
— Packed Double Precision Floating-Point Horizontal Subtract</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op/En</th>
<th>64/32-bit Mode</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>66 0F 7D /r HSUBPD xmm1, xmm2/m128</td>
<td>RM</td>
<td>V/V</td>
<td>SSE3</td>
<td>Horizontal subtract packed double precision floating-point values from xmm2/m128 to xmm1.</td></tr>
<tr>
<td>VEX.128.66.0F.WIG 7D /r VHSUBPD xmm1,xmm2, xmm3/m128</td>
<td>RVM</td>
<td>V/V</td>
<td>AVX</td>
<td>Horizontal subtract packed double precision floating-point values from xmm2 and xmm3/mem.</td></tr>
<tr>
<td>VEX.256.66.0F.WIG 7D /r VHSUBPD ymm1, ymm2, ymm3/m256</td>
<td>RVM</td>
<td>V/V</td>
<td>AVX</td>
<td>Horizontal subtract packed double precision floating-point values from ymm2 and ymm3/mem.</td></tr></table>
<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
</a></h2>
<table>
<tr>
<th>Op/En</th>
<th>Operand 1</th>
<th>Operand 2</th>
<th>Operand 3</th>
<th>Operand 4</th></tr>
<tr>
<td>RM</td>
<td>ModRM:reg (r, w)</td>
<td>ModRM:r/m (r)</td>
<td>N/A</td>
<td>N/A</td></tr>
<tr>
<td>RVM</td>
<td>ModRM:reg (w)</td>
<td>VEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>N/A</td></tr></table>
<h2 id="description">Description<a class="anchor" href="#description">
</a></h2>
<p>The HSUBPD instruction subtracts horizontally the packed double precision floating-point numbers of both operands.</p>
<p>Subtracts the double precision floating-point value in the high quadword of the destination operand from the low quadword of the destination operand and stores the result in the low quadword of the destination operand.</p>
<p>Subtracts the double precision floating-point value in the high quadword of the source operand from the low quadword of the source operand and stores the result in the high quadword of the destination operand.</p>
<p>In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).</p>
<p>See <a href='hsubpd.html#fig-3-21'>Figure 3-21</a> for HSUBPD; see <a href='hsubpd.html#fig-3-22'>Figure 3-22</a> for VHSUBPD.</p>
<figure id="fig-3-21">
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.1993722000000275pt; fill: #000" textLength="28.097765799999962" x="213.8376" y="42.23208699999992">[127:64]</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.1993722000000275pt; fill: #000" textLength="21.605891300000053" x="429.88772079" y="46.89675779999993">/m128</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.199372199999999pt; fill: #000" textLength="24.19486640000008" x="429.88796083" y="141.43286075">Result:</text>
<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.199372199999999pt; fill: #000" textLength="66.97126579999994" x="194.4007" y="141.43318699999998">xmm2/m128[63:0] -</text>
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<figcaption><a href='hsubpd.html#fig-3-21'>Figure 3-21</a>. HSUBPD—Packed Double Precision Floating-Point Horizontal Subtract</figcaption></figure>
<figure id="fig-3-22">
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<figcaption><a href='hsubpd.html#fig-3-22'>Figure 3-22</a>. VHSUBPD operation</figcaption></figure>
<p>128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding YMM register destination are unmodified.</p>
<p>VEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding YMM register destination are zeroed.</p>
<p>VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM register or a 256-bit memory location. The destination operand is a YMM register.</p>
<h2 id="operation">Operation<a class="anchor" href="#operation">
</a></h2>
<h3 id="hsubpd--128-bit-legacy-sse-version-">HSUBPD (128-bit Legacy SSE Version)<a class="anchor" href="#hsubpd--128-bit-legacy-sse-version-">
</a></h3>
<pre>DEST[63:0] := SRC1[63:0] - SRC1[127:64]
DEST[127:64] := SRC2[63:0] - SRC2[127:64]
DEST[MAXVL-1:128] (Unmodified)
</pre>
<h3 id="vhsubpd--vex-128-encoded-version-">VHSUBPD (VEX.128 Encoded Version)<a class="anchor" href="#vhsubpd--vex-128-encoded-version-">
</a></h3>
<pre>DEST[63:0] := SRC1[63:0] - SRC1[127:64]
DEST[127:64] := SRC2[63:0] - SRC2[127:64]
DEST[MAXVL-1:128] := 0
</pre>
<h3 id="vhsubpd--vex-256-encoded-version-">VHSUBPD (VEX.256 Encoded Version)<a class="anchor" href="#vhsubpd--vex-256-encoded-version-">
</a></h3>
<pre>DEST[63:0] := SRC1[63:0] - SRC1[127:64]
DEST[127:64] := SRC2[63:0] - SRC2[127:64]
DEST[191:128] := SRC1[191:128] - SRC1[255:192]
DEST[255:192] := SRC2[191:128] - SRC2[255:192]
</pre>
<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
</a></h2>
<pre>HSUBPD __m128d _mm_hsub_pd(__m128d a, __m128d b)
</pre>
<pre>VHSUBPD __m256d _mm256_hsub_pd (__m256d a, __m256d b);
</pre>
<h2 class="exceptions" id="exceptions">Exceptions<a class="anchor" href="#exceptions">
</a></h2>
<p>When the source operand is a memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated.</p>
<h2 class="exceptions" id="numeric-exceptions">Numeric Exceptions<a class="anchor" href="#numeric-exceptions">
</a></h2>
<p>Overflow, Underflow, Invalid, Precision, Denormal.</p>
<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
</a></h2>
<p>See <span class="not-imported">Table 2-19</span>, “Type 2 Class Exception Conditions.”</p><footer><p>
This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
</p></footer></body></html>
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