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<!DOCTYPE html>
<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>HADDPS
— Packed Single Precision Floating-Point Horizontal Add</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>HADDPS
— Packed Single Precision Floating-Point Horizontal Add</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op/En</th>
<th>64/32-bit Mode</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>F2 0F 7C /r HADDPS xmm1, xmm2/m128</td>
<td>RM</td>
<td>V/V</td>
<td>SSE3</td>
<td>Horizontal add packed single precision floating-point values from xmm2/m128 to xmm1.</td></tr>
<tr>
<td>VEX.128.F2.0F.WIG 7C /r VHADDPS xmm1, xmm2, xmm3/m128</td>
<td>RVM</td>
<td>V/V</td>
<td>AVX</td>
<td>Horizontal add packed single precision floating-point values from xmm2 and xmm3/mem.</td></tr>
<tr>
<td>VEX.256.F2.0F.WIG 7C /r VHADDPS ymm1, ymm2, ymm3/m256</td>
<td>RVM</td>
<td>V/V</td>
<td>AVX</td>
<td>Horizontal add packed single precision floating-point values from ymm2 and ymm3/mem.</td></tr></table>
<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
</a></h2>
<table>
<tr>
<th>Op/En</th>
<th>Operand 1</th>
<th>Operand 2</th>
<th>Operand 3</th>
<th>Operand 4</th></tr>
<tr>
<td>RM</td>
<td>ModRM:reg (r, w)</td>
<td>ModRM:r/m (r)</td>
<td>N/A</td>
<td>N/A</td></tr>
<tr>
<td>RVM</td>
<td>ModRM:reg (w)</td>
<td>VEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>N/A</td></tr></table>
<h2 id="description">Description<a class="anchor" href="#description">
</a></h2>
<p>Adds the single precision floating-point values in the first and second dwords of the destination operand and stores the result in the first dword of the destination operand.</p>
<p>Adds single precision floating-point values in the third and fourth dword of the destination operand and stores the result in the second dword of the destination operand.</p>
<p>Adds single precision floating-point values in the first and second dword of the source operand and stores the result in the third dword of the destination operand.</p>
<p>Adds single precision floating-point values in the third and fourth dword of the source operand and stores the result in the fourth dword of the destination operand.</p>
<p>In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).</p>
<p>See <a href='haddps.html#fig-3-19'>Figure 3-19</a> for HADDPS; see <a href='haddps.html#fig-3-20'>Figure 3-20</a> for VHADDPS.</p>
<figure id="fig-3-19">
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.408277799999951pt; fill: #000" textLength="105.79596720000018" x="229.221" y="19.268063000000097">HADDPS xmm1, xmm2/m128</text>
<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.408277799999951pt; fill: #000" textLength="24.00090000000006" x="432.59982642000006" y="39.78163223000013">xmm2/</text>
<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.408277799999951pt; fill: #000" textLength="28.913084200000014" x="174.8588" y="44.58206300000006">[127:96]</text>
<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.408277799999951pt; fill: #000" textLength="24.46491740000002" x="245.13660000000002" y="44.58206300000006">[95:64]</text>
<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.408277799999951pt; fill: #000" textLength="24.464917400000047" x="312.6394" y="44.58206300000006">[63:32]</text>
<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.408277799999951pt; fill: #000" textLength="20.016750600000023" x="382.36220000000003" y="44.58206300000006">[31:0]</text>
<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.408277799999951pt; fill: #000" textLength="20.008750300000088" x="432.59982642000006" y="49.38199223000015">m128</text>
<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.408277799999951pt; fill: #000" textLength="21.776816600000075" x="432.59909832000005" y="103.9778902600001">xmm1</text>
<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.408277799999951pt; fill: #000" textLength="28.913084200000014" x="174.8588" y="103.97836300000006">[127:96]</text>
<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.408277799999951pt; fill: #000" textLength="24.46491740000002" x="245.13660000000002" y="103.97836300000006">[95:64]</text>
<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.408277799999951pt; fill: #000" textLength="24.464917400000047" x="312.6394" y="103.97836300000006">[63:32]</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.063515733038685pt; fill: #000" textLength="40.20614563452435" x="169.92860000000002" y="162.7515772180758">xmm2/m128</text>
<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.063515733038685pt; fill: #000" textLength="40.20614563452432" x="238.0063" y="162.7515772180758">xmm2/m128</text>
<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.408277799999951pt; fill: #000" textLength="32.30521139999996" x="432.59982642000006" y="167.58722476000014">RESULT:</text>
<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.063515733038685pt; fill: #000" textLength="48.51457826360098" x="301.4889" y="167.5518772180758">xmm1[95:64] +</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.408277799999951pt; fill: #000" textLength="21.776816600000075" x="432.59982642000006" y="177.18758476000016">xmm1</text>
<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.063515733038685pt; fill: #000" textLength="46.18041431726209" x="302.5689405" y="177.1522372180758">xmm1[127:96]</text>
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<figcaption><a href='haddps.html#fig-3-19'>Figure 3-19</a>. HADDPS—Packed Single Precision Floating-Point Horizontal Add</figcaption></figure>
<figure id="fig-3-20">
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<figcaption><a href='haddps.html#fig-3-20'>Figure 3-20</a>. VHADDPS Operation</figcaption></figure>
<p>128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding YMM register destination are unmodified.</p>
<p>VEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding YMM register destination are zeroed.</p>
<p>VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM register or a 256-bit memory location. The destination operand is a YMM register.</p>
<h2 id="operation">Operation<a class="anchor" href="#operation">
</a></h2>
<h3 id="haddps--128-bit-legacy-sse-version-">HADDPS (128-bit Legacy SSE Version)<a class="anchor" href="#haddps--128-bit-legacy-sse-version-">
</a></h3>
<pre>DEST[31:0] := SRC1[63:32] + SRC1[31:0]
DEST[63:32] := SRC1[127:96] + SRC1[95:64]
DEST[95:64] := SRC2[63:32] + SRC2[31:0]
DEST[127:96] := SRC2[127:96] + SRC2[95:64]
DEST[MAXVL-1:128] (Unmodified)
</pre>
<h3 id="vhaddps--vex-128-encoded-version-">VHADDPS (VEX.128 Encoded Version)<a class="anchor" href="#vhaddps--vex-128-encoded-version-">
</a></h3>
<pre>DEST[31:0] := SRC1[63:32] + SRC1[31:0]
DEST[63:32] := SRC1[127:96] + SRC1[95:64]
DEST[95:64] := SRC2[63:32] + SRC2[31:0]
DEST[127:96] := SRC2[127:96] + SRC2[95:64]
DEST[MAXVL-1:128] := 0
</pre>
<h3 id="vhaddps--vex-256-encoded-version-">VHADDPS (VEX.256 Encoded Version)<a class="anchor" href="#vhaddps--vex-256-encoded-version-">
</a></h3>
<pre>DEST[31:0] := SRC1[63:32] + SRC1[31:0]
DEST[63:32] := SRC1[127:96] + SRC1[95:64]
DEST[95:64] := SRC2[63:32] + SRC2[31:0]
DEST[127:96] := SRC2[127:96] + SRC2[95:64]
DEST[159:128] := SRC1[191:160] + SRC1[159:128]
DEST[191:160] := SRC1[255:224] + SRC1[223:192]
DEST[223:192] := SRC2[191:160] + SRC2[159:128]
DEST[255:224] := SRC2[255:224] + SRC2[223:192]
</pre>
<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
</a></h2>
<pre>HADDPS __m128 _mm_hadd_ps (__m128 a, __m128 b);
</pre>
<pre>VHADDPS __m256 _mm256_hadd_ps (__m256 a, __m256 b);
</pre>
<h2 class="exceptions" id="exceptions">Exceptions<a class="anchor" href="#exceptions">
</a></h2>
<p>When the source operand is a memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated.</p>
<h2 class="exceptions" id="numeric-exceptions">Numeric Exceptions<a class="anchor" href="#numeric-exceptions">
</a></h2>
<p>Overflow, Underflow, Invalid, Precision, Denormal.</p>
<h2 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
</a></h2>
<p>See <span class="not-imported">Table 2-19</span>, “Type 2 Class Exception Conditions.”</p><footer><p>
This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
</p></footer></body></html>
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