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231 lines
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231 lines
8.2 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>ESETCONTEXT
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— Set the ENCLAVECONTEXT Field in SECS</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>ESETCONTEXT
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— Set the ENCLAVECONTEXT Field in SECS</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>EAX = 02H ENCLV[ESETCONTEXT]</td>
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<td>IR</td>
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<td>V/V</td>
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<td>EAX[5]</td>
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<td>This leaf function sets the ENCLAVECONTEXT field in SECS.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<td>Op/En</td>
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<td colspan="2">EAX</td>
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<td>RCX</td>
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<td>RDX</td></tr>
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<tr>
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<td>IR</td>
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<td>ESETCONTEXT (In)</td>
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<td>Return error code (Out)</td>
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<td>Address of the destination EPC page (In, EA)</td>
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<td>Context Value (In, EA)</td></tr></table>
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<h3 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h3>
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<p>The ESETCONTEXT leaf overwrites the ENCLAVECONTEXT field in the SECS. ECREATE and ELD of an SECS set the ENCLAVECONTEXT field in the SECS to the address of the SECS (for access later in ERDINFO). The ESETCONTEXT instruction allows a VMM to overwrite the default context value if necessary, for example, if the VMM is emulating ECREATE or ELD on behalf of the guest.</p>
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<p>The content of RCX is an effective address of the SECS page to be updated, RDX contains the address pointing to the value to be stored in the SECS. The DS segment is used to create linear address. Segment override is not supported.</p>
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<p>The instruction fails if:</p>
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<ul>
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<li>The operand is not properly aligned.</li>
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<li>RCX does not refer to an SECS page.</li></ul>
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<h2 id="esetcontext-memory-parameter-semantics">ESETCONTEXT Memory Parameter Semantics<a class="anchor" href="#esetcontext-memory-parameter-semantics">
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¶
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</a></h2>
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<table>
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<tr>
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<td>EPCPAGE</td>
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<td>CONTEXT</td></tr>
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<tr>
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<td>Read access permitted by Enclave</td>
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<td>Read/Write access permitted by Non Enclave</td></tr></table>
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<p>The instruction faults if any of the following:</p>
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<h2 id="esetcontext-faulting-conditions">ESETCONTEXT Faulting Conditions<a class="anchor" href="#esetcontext-faulting-conditions">
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¶
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</a></h2>
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<table>
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<tr>
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<td>A memory operand effective address is outside the DS segment limit (32b mode).</td>
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<td>A memory operand is not properly aligned.</td></tr>
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<tr>
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<td>DS segment is unusable (32b mode).</td>
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<td>A page fault occurs in accessing memory operands.</td></tr>
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<tr>
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<td>A memory address is in a non-canonical form (64b mode).</td>
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<td></td></tr></table>
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<h3 id="concurrency-restrictions">Concurrency Restrictions<a class="anchor" href="#concurrency-restrictions">
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¶
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</a></h3>
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<figure id="tbl-38-80">
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<table>
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<tr>
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<th rowspan="2">Leaf</th>
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<th rowspan="2">Parameter</th>
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<th colspan="3">Base Concurrency Restrictions</th></tr>
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<tr>
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<th>Access</th>
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<th>On Conflict</th>
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<th>SGX_CONFLICT VM Exit Qualification</th></tr>
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<tr>
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<td>ESETCONTEXT</td>
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<td>SECS [DS:RCX]</td>
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<td>Shared</td>
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<td>SGX_EPC_PAGE_ CONFLICT</td>
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<td></td></tr></table>
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<figcaption><span class="not-imported">Table 38-80</span>. Base Concurrency Restrictions of ESETCONTEXT</figcaption></figure>
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<figure id="tbl-38-81">
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<table>
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<tr>
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<th rowspan="3">Leaf</th>
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<th rowspan="3">Parameter</th>
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<th colspan="6">Additional Concurrency Restrictions</th></tr>
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<tr>
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<th colspan="2">vs. EACCEPT, EACCEPTCOPY, vs. EADD, EEXTEND, EINIT
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vs. ETRACK, ETRACKC
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Access vs. ETRACK, ETRACKC
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Access On Conflict
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Access vs. ETRACK, ETRACKC
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Access On Conflict
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EMODPE, EMODPR, EMODT</th>
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<th colspan="2">vs. EADD, EEXTEND, EINIT vs. EADD, EEXTEND, EINIT
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vs. ETRACK, ETRACKC
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</th>
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<th colspan="2">vs. ETRACK, ETRACKC</th></tr>
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<tr>
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<th>Access On Conflict
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Access On Conflict
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Access Access On Conflict
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Access On Conflict
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</th>
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<th></th>
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<th></th>
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<th></th>
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<th></th>
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<th></th></tr>
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<tr>
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<td>ESETCONTEXT</td>
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<td>SECS [DS:RCX]</td>
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<td>Concurrent</td>
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<td></td>
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<td>Concurrent</td>
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<td></td>
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<td>Concurrent</td>
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<td></td></tr></table>
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<figcaption><span class="not-imported">Table 38-81</span>. Additional Concurrency Restrictions of ESETCONTEXT</figcaption></figure>
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<h3 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h3>
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<h2 id="temp-variables-in-esetcontext-operational-flow">Temp Variables in ESETCONTEXT Operational Flow<a class="anchor" href="#temp-variables-in-esetcontext-operational-flow">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Name</th>
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<th>Type</th>
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<th>Size (bits)</th>
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<th>Description</th></tr>
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<tr>
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<td>TMP_SECS</td>
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<td>Physical Address</td>
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<td>64</td>
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<td>Physical address of the SECS of the page being modified.</td></tr>
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<tr>
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<td>TMP_CONTEXT</td>
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<td>CONTEXT</td>
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<td>64</td>
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<td>Data Value of CONTEXT.</td></tr></table>
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<h2 id="esetcontext-return-value-in-rax">ESETCONTEXT Return Value in RAX<a class="anchor" href="#esetcontext-return-value-in-rax">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Error</th>
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<th>Value</th>
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<th>Description</th></tr>
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<tr>
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<td>No Error</td>
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<td>0</td>
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<td>ESETCONTEXT Successful.</td></tr>
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<tr>
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<td>SGX_EPC_PAGE_CONFLICT</td>
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<td></td>
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<td>Failure due to concurrent operation of another SGX instruction.</td></tr></table>
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<p>(* check alignment of the EPCPAGE (RCX) *)</p>
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<p>IF (DS:RCX is not 4KByte Aligned) THEN</p>
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<p>#GP(0); FI;</p>
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<p>(* check that EPCPAGE (DS:RCX) is the address of an EPC page *)</p>
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<p>IF (DS:RCX does not resolve within an EPC)THEN</p>
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<p>#PF(DS:RCX, PFEC.SGX); FI;</p>
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<p>(* check alignment of the CONTEXT field (RDX) *)</p>
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<p>IF (DS:RDX is not 8Byte Aligned) THEN</p>
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<p>#GP(0); FI;</p>
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<p>(* Load CONTEXT into local variable *)</p>
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<p>TMP_CONTEXT := DS:RDX</p>
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<p>(* Check the EPC page for concurrency *)</p>
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<p>IF (EPC page is being modified) THEN</p>
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<p>RFLAGS.ZF := 1;</p>
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<p>RFLAGS.CF := 0;</p>
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<p>RAX := SGX_EPC_PAGE_CONFLICT;</p>
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<p>goto DONE;</p>
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<p>FI;</p>
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<p>(* check page validity *)</p>
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<p>IF (EPCM(DS:RCX).VALID = 0) THEN</p>
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<p>#PF(DS:RCX, PFEC.SGX);</p>
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<p>FI;</p>
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<p>(* check EPC page is an SECS page *)</p>
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<p>IF (EPCM(DS:RCX).PT is not PT_SECS) THEN</p>
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<p>#PF(DS:RCX, PFEC.SGX);</p>
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<p>FI;</p>
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<p>(* load the context value into SECS(DS:RCX).ENCLAVECONTEXT *)</p>
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<p>SECS(DS:RCX).ENCLAVECONTEXT := TMP_CONTEXT;</p>
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<p>RAX := 0;</p>
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<p>RFLAGS.ZF := 0;</p>
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<p>DONE:</p>
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<p>(* clear flags *)</p>
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<p>RFLAGS.CF,PF,AF,OF,SF := 0;</p>
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<h3 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
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¶
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</a></h3>
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<p>ZF is set if ESETCONTEXT fails due to concurrent operation with another SGX instruction; otherwise cleared.</p>
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<p>CF, PF, AF, OF, and SF are cleared.</p>
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<h3 class="exceptions" id="protected-mode-exceptions">Protected Mode Exceptions<a class="anchor" href="#protected-mode-exceptions">
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¶
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</a></h3>
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<table>
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<tr>
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<td rowspan="3">#GP(0)</td>
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<td>If a memory operand effective address is outside the DS segment limit.</td></tr>
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<tr>
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<td>If DS segment is unusable.</td></tr>
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<tr>
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<td>If a memory operand is not properly aligned.</td></tr>
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<tr>
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<td>#PF(error</td>
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<td>code) If a page fault occurs in accessing memory operands.</td></tr></table>
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<h3 class="exceptions" id="64-bit-mode-exceptions">64-Bit Mode Exceptions<a class="anchor" href="#64-bit-mode-exceptions">
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¶
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</a></h3>
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<table>
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<tr>
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<td rowspan="2">#GP(0)</td>
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<td>If a memory address is in a non-canonical form.</td></tr>
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<tr>
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<td>If a memory operand is not properly aligned.</td></tr>
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<tr>
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<td>#PF(error</td>
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<td>code) If a page fault occurs in accessing memory operands.</td></tr></table><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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