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265 lines
9.3 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>EREMOVE
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— Remove a page from the EPC</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>EREMOVE
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— Remove a page from the EPC</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>EAX = 03H ENCLS[EREMOVE]</td>
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<td>IR</td>
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<td>V/V</td>
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<td>SGX1</td>
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<td>This leaf function removes a page from the EPC.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<td>Op/En</td>
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<td colspan="2">EAX</td>
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<td>RCX</td></tr>
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<tr>
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<td>IR</td>
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<td>EREMOVE (In)</td>
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<td>Return error code (Out)</td>
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<td>Effective address of the EPC page (In)</td></tr></table>
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<h3 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h3>
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<p>This leaf function causes an EPC page to be un-associated with its SECS and be marked as unused. This instruction leaf can only be executed when the current privilege level is 0.</p>
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<p>The content of RCX is an effective address of an EPC page. The DS segment is used to create linear address. Segment override is not supported.</p>
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<p>The instruction fails if the operand is not properly aligned or does not refer to an EPC page or the page is in use by another thread, or other threads are running in the enclave to which the page belongs. In addition the instruction fails if the operand refers to an SECS with associations.</p>
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<h2 id="eremove-memory-parameter-semantics">EREMOVE Memory Parameter Semantics<a class="anchor" href="#eremove-memory-parameter-semantics">
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¶
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</a></h2>
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<table>
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<tr>
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<td>EPCPAGE</td></tr>
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<tr>
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<td>Write access permitted by Enclave</td></tr></table>
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<p>The instruction faults if any of the following:</p>
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<h2 id="eremove-faulting-conditions">EREMOVE Faulting Conditions<a class="anchor" href="#eremove-faulting-conditions">
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¶
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</a></h2>
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<table>
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<tr>
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<td>The memory operand is not properly aligned.</td>
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<td>The memory operand does not resolve in an EPC page.</td></tr>
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<tr>
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<td>Refers to an invalid SECS.</td>
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<td>Refers to an EPC page that is locked by another thread.</td></tr>
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<tr>
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<td>Another Intel SGX instruction is accessing the EPC page.</td>
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<td>RCX does not contain an effective address of an EPC page.</td></tr>
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<tr>
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<td>the EPC page refers to an SECS with associations.</td>
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<td></td></tr></table>
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<p>The error codes are:</p>
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<figure id="tbl-38-42">
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<table>
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<tr>
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<th>Error Code (see <span class="not-imported">Table 38-4</span>)</th>
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<th>Description</th></tr>
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<tr>
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<td>No Error</td>
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<td>EREMOVE successful.</td></tr>
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<tr>
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<td>SGX_CHILD_PRESENT</td>
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<td>If the SECS still have enclave pages loaded into EPC.</td></tr>
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<tr>
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<td>SGX_ENCLAVE_ACT</td>
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<td>If there are still logical processors executing inside the enclave.</td></tr></table>
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<figcaption><span class="not-imported">Table 38-42</span>. EREMOVE Return Value in RAX</figcaption></figure>
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<h3 id="concurrency-restrictions">Concurrency Restrictions<a class="anchor" href="#concurrency-restrictions">
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¶
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</a></h3>
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<figure id="tbl-38-43">
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<table>
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<tr>
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<th rowspan="2">Leaf</th>
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<th rowspan="2">Parameter</th>
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<th colspan="3">Base Concurrency Restrictions</th></tr>
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<tr>
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<th></th>
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<th>On Conflict </th>
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<th></th></tr>
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<tr>
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<td>EREMOVE EREMOVE
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Target [DS:RCX]
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Exclusive #GP EREMOVE
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Target [DS:RCX]
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</td>
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<td>Target [DS:RCX]</td>
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<td></td>
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<td></td>
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<td></td></tr></table>
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<figcaption><span class="not-imported">Table 38-43</span>. Base Concurrency Restrictions of EREMOVE</figcaption></figure>
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<figure id="tbl-38-44">
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<table>
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<tr>
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<th rowspan="3">Leaf</th>
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<th rowspan="3">Parameter</th>
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<th colspan="6">Additional Concurrency Restrictions</th></tr>
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<tr>
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<th colspan="2">vs. EACCEPT, EACCEPTCOPY, vs. EADD, EEXTEND, EINIT
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vs. ETRACK, ETRACKC
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Access vs. ETRACK, ETRACKC
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Access On Conflict
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Access vs. ETRACK, ETRACKC
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Access On Conflict
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EMODPE, EMODPR, EMODT</th>
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<th colspan="2">vs. EADD, EEXTEND, EINIT vs. EADD, EEXTEND, EINIT
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vs. ETRACK, ETRACKC
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</th>
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<th colspan="2">vs. ETRACK, ETRACKC</th></tr>
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<tr>
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<th>Access On Conflict
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Access On Conflict
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Access Access On Conflict
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Access On Conflict
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</th>
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<th></th>
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<th></th>
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<th></th>
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<th></th>
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<th></th></tr>
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<tr>
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<td>EREMOVE</td>
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<td>Target [DS:RCX]</td>
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<td>Concurrent</td>
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<td></td>
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<td>Concurrent</td>
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<td></td>
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<td>Concurrent</td>
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<td></td></tr></table>
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<figcaption><span class="not-imported">Table 38-44</span>. Additional Concurrency Restrictions of EREMOVE</figcaption></figure>
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<h3 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h3>
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<h2 id="temp-variables-in-eremove-operational-flow">Temp Variables in EREMOVE Operational Flow<a class="anchor" href="#temp-variables-in-eremove-operational-flow">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Name</th>
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<th>Type</th>
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<th>Size (Bits)</th>
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<th>Description</th></tr>
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<tr>
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<td>TMP_SECS</td>
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<td>Effective Address</td>
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<td>32/64</td>
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<td>Effective address of the SECS destination page.</td></tr></table>
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<p>IF (DS:RCX is not 4KByte Aligned)</p>
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<p>THEN #GP(0); FI;</p>
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<p>IF (DS:RCX does not resolve to an EPC page)</p>
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<p>THEN #PF(DS:RCX); FI;</p>
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<p>TMP_SECS := Get_SECS_ADDRESS();</p>
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<p>(* Check the EPC page for concurrency *)</p>
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<p>IF (EPC page being referenced by another Intel SGX instruction)</p>
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<p>THEN</p>
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<p>IF (<<VMX non-root operation>> AND <<ENABLE_EPC_VIRTUALIZATION_EXTENSIONS>>)</p>
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<p>THEN</p>
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<p>VMCS.Exit_reason := SGX_CONFLICT;</p>
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<p>VMCS.Exit_qualification.code := EPC_PAGE_CONFLICT_EXCEPTION;</p>
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<p>VMCS.Exit_qualification.error := 0;</p>
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<p>VMCS.Guest-physical_address := << translation of DS:RCX produced by paging >>;</p>
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<p>VMCS.Guest-linear_address := DS:RCX;</p>
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<p>Deliver VMEXIT;</p>
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<p>ELSE</p>
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<p>#GP(0);</p>
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<p>FI;</p>
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<p>FI;</p>
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<p>(* if DS:RCX is already unused, nothing to do*)</p>
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<p>IF ( (EPCM(DS:RCX).VALID = 0) or (EPCM(DS:RCX).PT = PT_TRIM AND EPCM(DS:RCX).MODIFIED = 0))</p>
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<p>THEN GOTO DONE;</p>
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<p>FI;</p>
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<p>IF ( (EPCM(DS:RCX).PT = PT_VA) OR</p>
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<p>((EPCM(DS:RCX).PT = PT_TRIM) AND (EPCM(DS:RCX).MODIFIED = 0)) )</p>
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<p>THEN</p>
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<p>EPCM(DS:RCX).VALID := 0;</p>
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<p>GOTO DONE;</p>
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<p>FI;</p>
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<p>IF (EPCM(DS:RCX).PT = PT_SECS)</p>
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<p>THEN</p>
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<p>IF (DS:RCX has an EPC page associated with it)</p>
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<p>THEN</p>
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<p>RFLAGS.ZF := 1;</p>
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<p>RAX := SGX_CHILD_PRESENT;</p>
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<p>GOTO ERROR_EXIT;</p>
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<p>FI;</p>
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<p>(* treat SECS as having a child page when VIRTCHILDCNT is non-zero *)</p>
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<p>IF (<<in VMX non-root operation>> AND</p>
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<p><<ENABLE_EPC_VIRTUALIZATION_EXTENSIONS>> AND</p>
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<p>(SECS(DS:RCX).VIRTCHILDCNT ≠ 0))</p>
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<p>THEN</p>
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<p>RFLAGS.ZF := 1;</p>
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<p>RAX := SGX_CHILD_PRESENT</p>
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<p>GOTO ERROR_EXIT</p>
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<p>FI;</p>
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<p>EPCM(DS:RCX).VALID := 0;</p>
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<p>GOTO DONE;</p>
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<p>FI;</p>
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<p>IF (Other threads active using SECS)</p>
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<p>THEN</p>
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<p>RFLAGS.ZF := 1;</p>
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<p>RAX := SGX_ENCLAVE_ACT;</p>
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<p>GOTO ERROR_EXIT;</p>
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<p>FI;</p>
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<p>IF ( (EPCM(DS:RCX).PT is PT_REG) or (EPCM(DS:RCX).PT is PT_TCS) or (EPCM(DS:RCX).PT is PT_TRIM) or</p>
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<p>(EPCM(DS:RCX).PT is PT_SS_FIRST) or (EPCM(DS:RCX).PT is PT_SS_REST))</p>
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<p>THEN</p>
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<p>EPCM(DS:RCX).VALID := 0;</p>
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<p>GOTO DONE;</p>
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<p>FI;</p>
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<p>DONE:</p>
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<p>RAX := 0;</p>
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<p>RFLAGS.ZF := 0;</p>
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<p>ERROR_EXIT:</p>
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<p>RFLAGS.CF,PF,AF,OF,SF := 0;</p>
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<h3 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
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¶
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</a></h3>
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<p>Sets ZF if unsuccessful, otherwise cleared and RAX returns error code. Clears CF, PF, AF, OF, SF.</p>
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<h3 class="exceptions" id="protected-mode-exceptions">Protected Mode Exceptions<a class="anchor" href="#protected-mode-exceptions">
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¶
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</a></h3>
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<table>
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<tr>
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<td rowspan="3">#GP(0)</td>
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<td>If a memory operand effective address is outside the DS segment limit.</td></tr>
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<tr>
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<td>If a memory operand is not properly aligned.</td></tr>
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<tr>
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<td>If another Intel SGX instruction is accessing the page.</td></tr>
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<tr>
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<td rowspan="2">#PF(error</td>
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<td>code) If a page fault occurs in accessing memory operands.</td></tr>
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<tr>
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<td>If the memory operand is not an EPC page.</td></tr></table>
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<h3 class="exceptions" id="64-bit-mode-exceptions">64-Bit Mode Exceptions<a class="anchor" href="#64-bit-mode-exceptions">
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¶
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</a></h3>
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<table>
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<tr>
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<td rowspan="3">#GP(0)</td>
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<td>If the memory operand is non-canonical form.</td></tr>
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<tr>
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<td>If a memory operand is not properly aligned.</td></tr>
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<tr>
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<td>If another Intel SGX instruction is accessing the page.</td></tr>
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<tr>
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<td rowspan="2">#PF(error</td>
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<td>code) If a page fault occurs in accessing memory operands.</td></tr>
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<tr>
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<td>If the memory operand is not an EPC page.</td></tr></table><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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