forked from NRZCode/ia32-64
82 lines
3.5 KiB
HTML
82 lines
3.5 KiB
HTML
<!DOCTYPE html>
|
||
<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>XSUSLDTRK
|
||
— Suspend Tracking Load Addresses</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>XSUSLDTRK
|
||
— Suspend Tracking Load Addresses</h1>
|
||
|
||
<table>
|
||
<tr>
|
||
<th>Opcode/Instruction</th>
|
||
<th>Op/En</th>
|
||
<th>64/32 bit Mode Support</th>
|
||
<th>CPUID Feature Flag</th>
|
||
<th>Description</th></tr>
|
||
<tr>
|
||
<td>F2 0F 01 E8 XSUSLDTRK</td>
|
||
<td>ZO</td>
|
||
<td>V/V</td>
|
||
<td>TSXLDTRK</td>
|
||
<td>Specifies the start of an Intel TSX suspend read address tracking region.</td></tr></table>
|
||
<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
|
||
¶
|
||
</a></h2>
|
||
<table>
|
||
<tr>
|
||
<th>Op/En</th>
|
||
<th>Tuple</th>
|
||
<th>Operand 1</th>
|
||
<th>Operand 2</th>
|
||
<th>Operand 3</th>
|
||
<th>Operand 4</th></tr>
|
||
<tr>
|
||
<td>ZO</td>
|
||
<td>N/A</td>
|
||
<td>N/A</td>
|
||
<td>N/A</td>
|
||
<td>N/A</td>
|
||
<td>N/A</td></tr></table>
|
||
<h3 id="description">Description<a class="anchor" href="#description">
|
||
¶
|
||
</a></h3>
|
||
<p>The instruction marks the start of an Intel TSX (RTM) suspend load address tracking region. If the instruction is used inside a transactional region, subsequent loads are not added to the read set of the transaction. If the instruction is used inside a suspend load address tracking region it will cause transaction abort.</p>
|
||
<p>If the instruction is used outside of a transactional region it behaves like a NOP.</p>
|
||
<p>Chapter 16, “Programming with Intel® Transactional Synchronization Extensions‚” in the Intel<sup>®</sup> 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 provides additional information on Intel<sup>®</sup> TSX Suspend Load Address Tracking.</p>
|
||
<h3 id="operation">Operation<a class="anchor" href="#operation">
|
||
¶
|
||
</a></h3>
|
||
<h4 id="xsusldtrk">XSUSLDTRK<a class="anchor" href="#xsusldtrk">
|
||
¶
|
||
</a></h4>
|
||
<pre>IF RTM_ACTIVE = 1:
|
||
IF SUSLDTRK_ACTIVE = 0:
|
||
SUSLDTRK_ACTIVE := 1
|
||
ELSE:
|
||
RTM_ABORT
|
||
ELSE:
|
||
NOP
|
||
</pre>
|
||
<h3 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
|
||
¶
|
||
</a></h3>
|
||
<p>None.</p>
|
||
<h3 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
|
||
¶
|
||
</a></h3>
|
||
<pre>XSUSLDTRK void _xsusldtrk(void);
|
||
</pre>
|
||
<h3 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
|
||
¶
|
||
</a></h3>
|
||
<p>None.</p>
|
||
<h3 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
|
||
¶
|
||
</a></h3>
|
||
<table>
|
||
<tr>
|
||
<td rowspan="2">#UD</td>
|
||
<td>If CPUID.(EAX=7, ECX=0):EDX.TSXLDTRK[bit 16] = 0.</td></tr>
|
||
<tr>
|
||
<td>If the LOCK prefix is used.</td></tr></table><footer><p>
|
||
This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
|
||
inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
|
||
ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
|
||
</p></footer></body></html>
|