forked from NRZCode/ia32-64
82 lines
3.5 KiB
HTML
82 lines
3.5 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>XRESLDTRK
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— Resume Tracking Load Addresses</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>XRESLDTRK
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— Resume Tracking Load Addresses</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>F2 0F 01 E9 XRESLDTRK</td>
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<td>ZO</td>
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<td>V/V</td>
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<td>TSXLDTRK</td>
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<td>Specifies the end of an Intel TSX suspend read address tracking region.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>ZO</td>
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<td>N/A</td>
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<td>N/A</td>
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<td>N/A</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h3 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h3>
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<p>The instruction marks the end of an Intel TSX (RTM) suspend load address tracking region. If the instruction is used inside a suspend load address tracking region it will end the suspend region and all following load addresses will be added to the transaction read set. If this instruction is used inside an active transaction but not in a suspend region it will cause transaction abort.</p>
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<p>If the instruction is used outside of a transactional region it behaves like a NOP.</p>
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<p>Chapter 16, “Programming with Intel® Transactional Synchronization Extensions‚” in the Intel<sup>®</sup> 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 provides additional information on Intel<sup>®</sup> TSX Suspend Load Address Tracking.</p>
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<h3 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h3>
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<h4 id="xresldtrk">XRESLDTRK<a class="anchor" href="#xresldtrk">
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¶
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</a></h4>
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<pre>IF RTM_ACTIVE = 1:
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IF SUSLDTRK_ACTIVE = 1:
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SUSLDTRK_ACTIVE := 0
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ELSE:
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RTM_ABORT
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ELSE:
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NOP
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</pre>
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<h3 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
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¶
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</a></h3>
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<p>None.</p>
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<h3 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h3>
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<pre>XRESLDTRK void _xresldtrk(void);
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</pre>
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<h3 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h3>
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<p>None.</p>
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<h3 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h3>
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<table>
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<tr>
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<td rowspan="2">#UD</td>
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<td>If CPUID.(EAX=7, ECX=0):EDX.TSXLDTRK[bit 16] = 0.</td></tr>
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<tr>
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<td>If the LOCK prefix is used.</td></tr></table><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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