forked from NRZCode/ia32-64
165 lines
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HTML
165 lines
7 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>XBEGIN
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— Transactional Begin</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>XBEGIN
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— Transactional Begin</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>C7 F8 XBEGIN rel16</td>
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<td>A</td>
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<td>V/V</td>
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<td>RTM</td>
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<td>Specifies the start of an RTM region. Provides a 16-bit relative offset to compute the address of the fallback instruction address at which execution resumes following an RTM abort.</td></tr>
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<tr>
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<td>C7 F8 XBEGIN rel32</td>
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<td>A</td>
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<td>V/V</td>
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<td>RTM</td>
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<td>Specifies the start of an RTM region. Provides a 32-bit relative offset to compute the address of the fallback instruction address at which execution resumes following an RTM abort.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Operand 1</th>
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<th>Operand2</th>
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<th>Operand3</th>
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<th>Operand4</th></tr>
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<tr>
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<td>A</td>
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<td>Offset</td>
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<td>N/A</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>The XBEGIN instruction specifies the start of an RTM code region. If the logical processor was not already in transactional execution, then the XBEGIN instruction causes the logical processor to transition into transactional execution. The XBEGIN instruction that transitions the logical processor into transactional execution is referred to as the outermost XBEGIN instruction. The instruction also specifies a relative offset to compute the address of the fallback code path following a transactional abort. (Use of the 16-bit operand size does not cause this address to be truncated to 16 bits, unlike a near jump to a relative offset.)</p>
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<p>On an RTM abort, the logical processor discards all architectural register and memory updates performed during the RTM execution and restores architectural state to that corresponding to the outermost XBEGIN instruction. The fallback address following an abort is computed from the outermost XBEGIN instruction.</p>
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<p>Execution of XBEGIN while in a suspend read address tracking region causes a transactional abort.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<h3 id="xbegin">XBEGIN<a class="anchor" href="#xbegin">
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¶
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</a></h3>
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<pre>IF RTM_NEST_COUNT < MAX_RTM_NEST_COUNT AND SUSLDTRK_ACTIVE = 0
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THEN
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RTM_NEST_COUNT++
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IF RTM_NEST_COUNT = 1 THEN
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IF 64-bit Mode
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THEN
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IF OperandSize = 16
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THEN fallbackRIP := RIP + SignExtend64(rel16);
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ELSE fallbackRIP := RIP + SignExtend64(rel32);
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FI;
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IF fallbackRIP is not canonical
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THEN #GP(0);
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FI;
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ELSE
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IF OperandSize = 16
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THEN fallbackEIP := EIP + SignExtend32(rel16);
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ELSE fallbackEIP := EIP + rel32;
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FI;
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IF fallbackEIP outside code segment limit
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THEN #GP(0);
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FI;
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FI;
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RTM_ACTIVE := 1
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Enter RTM Execution (* record register state, start tracking memory state*)
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FI; (* RTM_NEST_COUNT = 1 *)
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ELSE (* RTM_NEST_COUNT = MAX_RTM_NEST_COUNT OR SUSLDTRK_ACTIVE = 1 *)
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GOTO RTM_ABORT_PROCESSING
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FI;
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(* For any RTM abort condition encountered during RTM execution *)
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RTM_ABORT_PROCESSING:
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Restore architectural register state
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Discard memory updates performed in transaction
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Update EAX with status
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RTM_NEST_COUNT := 0
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RTM_ACTIVE := 0
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SUSLDTRK_ACTIVE := 0
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IF 64-bit mode
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THEN
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RIP := fallbackRIP
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ELSE
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EIP := fallbackEIP
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FI;
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END
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</pre>
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<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
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¶
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</a></h2>
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<p>None.</p>
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<h2 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h2>
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<pre>XBEGIN unsigned int _xbegin( void );
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</pre>
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<h2 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h2>
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<p>None.</p>
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<h2 class="exceptions" id="protected-mode-exceptions">Protected Mode Exceptions<a class="anchor" href="#protected-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td rowspan="2">#UD</td>
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<td>CPUID.(EAX=7, ECX=0):EBX.RTM[bit 11]=0.</td></tr>
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<tr>
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<td>If LOCK prefix is used.</td></tr>
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<tr>
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<td>#GP(0)</td>
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<td>If the fallback address is outside the CS segment.</td></tr></table>
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<h2 class="exceptions" id="real-address-mode-exceptions">Real-Address Mode Exceptions<a class="anchor" href="#real-address-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td>#GP(0)</td>
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<td>If the fallback address is outside the address space 0000H and FFFFH.</td></tr>
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<tr>
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<td rowspan="2">#UD</td>
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<td>CPUID.(EAX=7, ECX=0):EBX.RTM[bit 11]=0.</td></tr>
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<tr>
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<td>If LOCK prefix is used.</td></tr></table>
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<h2 class="exceptions" id="virtual-8086-mode-exceptions">Virtual-8086 Mode Exceptions<a class="anchor" href="#virtual-8086-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td>#GP(0)</td>
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<td>If the fallback address is outside the address space 0000H and FFFFH.</td></tr>
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<tr>
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<td rowspan="2">#UD</td>
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<td>CPUID.(EAX=7, ECX=0):EBX.RTM[bit 11]=0.</td></tr>
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<tr>
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<td>If LOCK prefix is used.</td></tr></table>
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<h2 class="exceptions" id="compatibility-mode-exceptions">Compatibility Mode Exceptions<a class="anchor" href="#compatibility-mode-exceptions">
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¶
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</a></h2>
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<p>Same exceptions as in protected mode.</p>
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<h2 class="exceptions" id="64-bit-mode-exceptions">64-bit Mode Exceptions<a class="anchor" href="#64-bit-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td rowspan="2">#UD</td>
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<td>CPUID.(EAX=7, ECX=0):EBX.RTM[bit 11] = 0.</td></tr>
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<tr>
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<td>If LOCK prefix is used.</td></tr>
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<tr>
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<td>#GP(0)</td>
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<td>If the fallback address is non-canonical.</td></tr></table><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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