forked from NRZCode/ia32-64
92 lines
3.9 KiB
HTML
92 lines
3.9 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>WRPKRU
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— Write Data to User Page Key Register</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>WRPKRU
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— Write Data to User Page Key Register</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>NP 0F 01 EF WRPKRU</td>
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<td>ZO</td>
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<td>V/V</td>
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<td>OSPKE</td>
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<td>Writes EAX into PKRU.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>ZO</td>
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<td>N/A</td>
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<td>N/A</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h2 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h2>
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<p>Writes the value of EAX into PKRU. ECX and EDX must be 0 when WRPKRU is executed; otherwise, a general-protection exception (#GP) occurs.</p>
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<p>WRPKRU can be executed only if CR4.PKE = 1; otherwise, an invalid-opcode exception (#UD) occurs. Software can discover the value of CR4.PKE by examining CPUID.(EAX=07H,ECX=0H):ECX.OSPKE [bit 4].</p>
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<p>On processors that support the Intel 64 Architecture, the high-order 32-bits of RCX, RDX, and RAX are ignored.</p>
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<p>WRPKRU will never execute speculatively. Memory accesses affected by PKRU register will not execute (even speculatively) until all prior executions of WRPKRU have completed execution and updated the PKRU register.</p>
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<h2 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h2>
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<pre>IF (ECX = 0 AND EDX = 0)
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THEN PKRU := EAX;
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ELSE #GP(0);
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FI;
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</pre>
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<h2 id="flags-affected">Flags Affected<a class="anchor" href="#flags-affected">
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¶
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</a></h2>
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<p>None.</p>
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<h2 id="c-c++-compiler-intrinsic-equivalent">C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h2>
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<pre>WRPKRU void _wrpkru(uint32_t);
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</pre>
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<h2 class="exceptions" id="protected-mode-exceptions">Protected Mode Exceptions<a class="anchor" href="#protected-mode-exceptions">
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¶
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</a></h2>
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<table>
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<tr>
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<td rowspan="2">#GP(0)</td>
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<td>If ECX ≠ 0.</td></tr>
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<tr>
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<td>If EDX ≠ 0.</td></tr>
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<tr>
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<td rowspan="2">#UD</td>
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<td>If the LOCK prefix is used.</td></tr>
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<tr>
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<td>If CR4.PKE = 0.</td></tr></table>
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<h2 class="exceptions" id="real-address-mode-exceptions">Real-Address Mode Exceptions<a class="anchor" href="#real-address-mode-exceptions">
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¶
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</a></h2>
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<p>Same exceptions as in protected mode.</p>
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<h2 class="exceptions" id="virtual-8086-mode-exceptions">Virtual-8086 Mode Exceptions<a class="anchor" href="#virtual-8086-mode-exceptions">
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¶
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</a></h2>
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<p>Same exceptions as in protected mode.</p>
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<h2 class="exceptions" id="compatibility-mode-exceptions">Compatibility Mode Exceptions<a class="anchor" href="#compatibility-mode-exceptions">
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¶
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</a></h2>
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<p>Same exceptions as in protected mode.</p>
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<h2 class="exceptions" id="64-bit-mode-exceptions">64-Bit Mode Exceptions<a class="anchor" href="#64-bit-mode-exceptions">
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¶
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</a></h2>
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<p>Same exceptions as in protected mode.</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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