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179 lines
8.8 KiB
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<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>VRNDSCALEPH
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— Round Packed FP16 Values to Include a Given Number of Fraction Bits</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>VRNDSCALEPH
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— Round Packed FP16 Values to Include a Given Number of Fraction Bits</h1>
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<table>
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<tr>
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<th> Instruction En bit Mode Flag
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Support Instruction En bit Mode Flag
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Support 64/32 CPUID Feature Instruction En bit Mode Flag CPUID Feature Instruction En bit Mode Flag Op/ 64/32 CPUID Feature Instruction En bit Mode Flag 64/32 CPUID Feature Instruction En bit Mode Flag CPUID Feature Instruction En bit Mode Flag Op/ 64/32 CPUID Feature </th>
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<th></th>
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<th>Support</th>
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<th></th>
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<th>Description</th></tr>
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<tr>
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<td>EVEX.128.NP.0F3A.W0 08 /r /ib VRNDSCALEPH xmm1{k1}{z}, xmm2/m128/m16bcst, imm8</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512-FP16 AVX512VL</td>
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<td>Round packed FP16 values in xmm2/m128/m16bcst to a number of fraction bits specified by the imm8 field. Store the result in xmm1 subject to writemask k1.</td></tr>
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<tr>
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<td>EVEX.256.NP.0F3A.W0 08 /r /ib VRNDSCALEPH ymm1{k1}{z}, ymm2/m256/m16bcst, imm8</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512-FP16 AVX512VL</td>
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<td>Round packed FP16 values in ymm2/m256/m16bcst to a number of fraction bits specified by the imm8 field. Store the result in ymm1 subject to writemask k1.</td></tr>
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<tr>
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<td>EVEX.512.NP.0F3A.W0 08 /r /ib VRNDSCALEPH zmm1{k1}{z}, zmm2/m512/m16bcst {sae}, imm8</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512-FP16</td>
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<td>Round packed FP16 values in zmm2/m512/m16bcst to a number of fraction bits specified by the imm8 field. Store the result in zmm1 subject to writemask k1.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>Full</td>
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<td>ModRM:reg (w)</td>
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<td>ModRM:r/m (r)</td>
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<td>imm8 (r)</td>
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<td>N/A</td></tr></table>
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<h3 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h3>
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<p>This instruction rounds the FP16 values in the source operand by the rounding mode specified in the immediate operand (see <a href='vrndscaleph.html#tbl-5-32'>Table 5-32</a>) and places the result in the destination operand. The destination operand is conditionally updated according to the writemask.</p>
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<p>The rounding process rounds the input to an integral value, plus number bits of fraction that are specified by imm8[7:4] (to be included in the result), and returns the result as an FP16 value.</p>
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<p>Note that no overflow is induced while executing this instruction (although the source is scaled by the imm8[7:4] value).</p>
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<p>The immediate operand also specifies control fields for the rounding operation. Three bit fields are defined and shown in <a href='vrndscaleph.html#tbl-5-32'>Table 5-32</a>, “Imm8 Controls for VRNDSCALEPH/VRNDSCALESH.” Bit 3 of the immediate byte controls the processor behavior for a precision exception, bit 2 selects the source of rounding mode control, and bits 1:0 specify a non-sticky rounding-mode value.</p>
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<p>The Precision Floating-Point Exception is signaled according to the immediate operand. If any source operand is an SNaN then it will be converted to a QNaN.</p>
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<p>The sign of the result of this instruction is preserved, including the sign of zero. Special cases are described in Table 5-33.</p>
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<p>The formula of the operation on each data element for VRNDSCALEPH is</p>
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<p>ROUND(x) = 2<sup>−M</sup> *Round_to_INT(x * 2<sup>M</sup>, round_ctrl),</p>
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<p>round_ctrl = imm[3:0];</p>
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<p>M=imm[7:4];</p>
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<p>The operation of x * 2<sup>M</sup> is computed as if the exponent range is unlimited (i.e., no overflow ever occurs).</p>
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<p>If this instruction encoding’s SPE bit (bit 3) in the immediate operand is 1, VRNDSCALEPH can set MXCSR.UE without MXCSR.PE.</p>
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<p>EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.</p>
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<figure id="tbl-5-32">
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<table>
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<tr>
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<th>Imm8 Bits</th>
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<th>Description</th></tr>
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<tr>
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<td>imm8[7:4]</td>
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<td>Number of fixed points to preserve.</td></tr>
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<tr>
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<td>imm8[3]</td>
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<td>Suppress Precision Exception (SPE) 0b00: Implies use of MXCSR exception mask. 0b01: Implies suppress.</td></tr>
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<tr>
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<td>imm8[2]</td>
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<td>Round Select (RS) 0b00: Implies use of imm8[1:0]. 0b01: Implies use of MXCSR.</td></tr>
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<tr>
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<td>imm8[1:0]</td>
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<td>Round Control Override: 0b00: Round nearest even. 0b01: Round down. 0b10: Round up. 0b11: Truncate.</td></tr></table>
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<figcaption><a href='vrndscaleph.html#tbl-5-32'>Table 5-32</a>. Imm8 Controls for VRNDSCALEPH/VRNDSCALESH</figcaption></figure>
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<figure id="tbl-5-33">
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<table>
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<tr>
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<th>Input Value</th>
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<th>Returned Value</th></tr>
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<tr>
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<td>Src1 = ±∞</td>
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<td>Src1</td></tr>
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<tr>
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<td>Src1 = ±NaN</td>
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<td>Src1 converted to QNaN</td></tr>
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<tr>
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<td>Src1 = ±0</td>
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<td>Src1</td></tr></table>
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<figcaption><a href='vrndscaleph.html#tbl-5-33'>Table 5-33</a>. VRNDSCALEPH/VRNDSCALESH Special Cases</figcaption></figure>
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<h3 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h3>
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<pre>def round_fp16_to_integer(src, imm8):
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if imm8[2] = 1:
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rounding_direction := MXCSR.RC
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else:
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rounding_direction := imm8[1:0]
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m := imm8[7:4] // scaling factor
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tsrc1 := 2^m * src
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if rounding_direction = 0b00:
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tmp := round_to_nearest_even_integer(trc1)
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else if rounding_direction = 0b01:
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tmp := round_to_equal_or_smaller_integer(trc1)
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else if rounding_direction = 0b10:
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tmp := round_to_equal_or_larger_integer(trc1)
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else if rounding_direction = 0b11:
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tmp := round_to_smallest_magnitude_integer(trc1)
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dst := 2^(-m) * tmp
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if imm8[3]==0: // check SPE
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if src != dst:
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MXCSR.PE := 1
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return dst
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</pre>
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<h4 id="vrndscaleph-dest-k1---src--imm8">VRNDSCALEPH dest{k1}, src, imm8<a class="anchor" href="#vrndscaleph-dest-k1---src--imm8">
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¶
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</a></h4>
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<pre>VL = 128, 256 or 512
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KL := VL/16
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FOR i := 0 to KL-1:
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IF k1[i] or *no writemask*:
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IF SRC is memory and (EVEX.b = 1):
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tsrc := src.fp16[0]
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ELSE:
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tsrc := src.fp16[i]
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DEST.fp16[i] := round_fp16_to_integer(tsrc, imm8)
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ELSE IF *zeroing*:
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DEST.fp16[i] := 0
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//else DEST.fp16[i] remains unchanged
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DEST[MAXVL-1:VL] := 0
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</pre>
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<h3 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h3>
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<pre>VRNDSCALEPH __m128h _mm_mask_roundscale_ph (__m128h src, __mmask8 k, __m128h a, int imm8);
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</pre>
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<pre>VRNDSCALEPH __m128h _mm_maskz_roundscale_ph (__mmask8 k, __m128h a, int imm8);
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</pre>
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<pre>VRNDSCALEPH __m128h _mm_roundscale_ph (__m128h a, int imm8);
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</pre>
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<pre>VRNDSCALEPH __m256h _mm256_mask_roundscale_ph (__m256h src, __mmask16 k, __m256h a, int imm8);
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</pre>
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<pre>VRNDSCALEPH __m256h _mm256_maskz_roundscale_ph (__mmask16 k, __m256h a, int imm8);
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</pre>
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<pre>VRNDSCALEPH __m256h _mm256_roundscale_ph (__m256h a, int imm8);
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</pre>
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<pre>VRNDSCALEPH __m512h _mm512_mask_roundscale_ph (__m512h src, __mmask32 k, __m512h a, int imm8);
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</pre>
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<pre>VRNDSCALEPH __m512h _mm512_maskz_roundscale_ph (__mmask32 k, __m512h a, int imm8);
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</pre>
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<pre>VRNDSCALEPH __m512h _mm512_roundscale_ph (__m512h a, int imm8);
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</pre>
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<pre>VRNDSCALEPH __m512h _mm512_mask_roundscale_round_ph (__m512h src, __mmask32 k, __m512h a, int imm8, const int sae);
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</pre>
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<pre>VRNDSCALEPH __m512h _mm512_maskz_roundscale_round_ph (__mmask32 k, __m512h a, int imm8, const int sae);
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</pre>
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<pre>VRNDSCALEPH __m512h _mm512_roundscale_round_ph (__m512h a, int imm8, const int sae);
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</pre>
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<h3 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h3>
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<p>Invalid, Underflow, Precision.</p>
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<h3 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h3>
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<p>EVEX-encoded instruction, see <span class="not-imported">Table 2-46</span>, “Type E2 Class Exception Conditions.”</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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