forked from NRZCode/ia32-64
221 lines
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221 lines
15 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>VRNDSCALEPD
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— Round Packed Float64 Values to Include a Given Number of Fraction Bits</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>VRNDSCALEPD
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— Round Packed Float64 Values to Include a Given Number of Fraction Bits</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>EVEX.128.66.0F3A.W1 09 /r ib VRNDSCALEPD xmm1 {k1}{z}, xmm2/m128/m64bcst, imm8</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512VL AVX512F</td>
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<td>Rounds packed double precision floating-point values in xmm2/m128/m64bcst to a number of fraction bits specified by the imm8 field. Stores the result in xmm1 register. Under writemask.</td></tr>
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<tr>
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<td>EVEX.256.66.0F3A.W1 09 /r ib VRNDSCALEPD ymm1 {k1}{z}, ymm2/m256/m64bcst, imm8</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512VL AVX512F</td>
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<td>Rounds packed double precision floating-point values in ymm2/m256/m64bcst to a number of fraction bits specified by the imm8 field. Stores the result in ymm1 register. Under writemask.</td></tr>
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<tr>
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<td>EVEX.512.66.0F3A.W1 09 /r ib VRNDSCALEPD zmm1 {k1}{z}, zmm2/m512/m64bcst{sae}, imm8</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512F</td>
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<td>Rounds packed double precision floating-point values in zmm2/m512/m64bcst to a number of fraction bits specified by the imm8 field. Stores the result in zmm1 register using writemask k1.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple Type</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>Full</td>
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<td>ModRM:reg (w)</td>
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<td>ModRM:r/m (r)</td>
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<td>imm8</td>
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<td>N/A</td></tr></table>
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<h3 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h3>
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<p>Round the double precision floating-point values in the source operand by the rounding mode specified in the immediate operand (see <a href='vrndscalepd.html#fig-5-29'>Figure 5-29</a>) and places the result in the destination operand.</p>
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<p>The destination operand (the first operand) is a ZMM/YMM/XMM register conditionally updated according to the writemask. The source operand (the second operand) can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 64-bit memory location.</p>
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<p>The rounding process rounds the input to an integral value, plus number bits of fraction that are specified by imm8[7:4] (to be included in the result) and returns the result as a double precision floating-point value.</p>
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<p>It should be noticed that no overflow is induced while executing this instruction (although the source is scaled by the imm8[7:4] value).</p>
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<p>The immediate operand also specifies control fields for the rounding operation, three bit fields are defined and shown in the “Immediate Control Description” figure below. Bit 3 of the immediate byte controls the processor behavior for a precision exception, bit 2 selects the source of rounding mode control. Bits 1:0 specify a non-sticky rounding-mode value (immediate control table below lists the encoded values for rounding-mode field).</p>
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<p>The Precision Floating-Point Exception is signaled according to the immediate operand. If any source operand is an SNaN then it will be converted to a QNaN. If DAZ is set to ‘1 then denormals will be converted to zero before rounding.</p>
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<p>The sign of the result of this instruction is preserved, including the sign of zero.</p>
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<p>The formula of the operation on each data element for VRNDSCALEPD is</p>
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<p>ROUND(x) = 2<sup>-M</sup>*Round_to_INT(x*2<sup>M</sup>, round_ctrl),</p>
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<p>round_ctrl = imm[3:0];</p>
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<p>M=imm[7:4];</p>
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<p>The operation of x*2<sup>M</sup> is computed as if the exponent range is unlimited (i.e., no overflow ever occurs).</p>
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<p>VRNDSCALEPD is a more general form of the VEX-encoded VROUNDPD instruction. In VROUNDPD, the formula of the operation on each element is</p>
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<p>ROUND(x) = Round_to_INT(x, round_ctrl),</p>
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<p>round_ctrl = imm[3:0];</p>
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<p>Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.</p>
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<figure id="fig-5-29">
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<svg style="width: 618.9840000000002pt; height: 129.671976pt" viewBox="41.06 0.0 520.8200000000002 113.05998">
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518pt; fill: #000" textLength="3.509999999999991" x="440.70000000000005" y="23.795979999999957">0</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000029pt; fill: #000" textLength="14.071200000000005" x="62.04000000000008" y="35.97598000000005">imm8</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000029pt; fill: #000" textLength="9.752400000000023" x="297.06" y="37.17597999999998">SPE</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000029pt; fill: #000" textLength="6.786000000000001" x="344.5800000000001" y="37.17597999999998">RS</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000029pt; fill: #000" textLength="59.56619999999998" x="390.6000000000001" y="37.65598">Round Control Override</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000029pt; fill: #000" textLength="46.021199999999965" x="164.10000000000008" y="37.65598">Fixed point length</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000029pt; fill: #000" textLength="98.2908000000001" x="223.56" y="62.55597999999998">Suppress Precision Exception: Imm8[3]</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000029pt; fill: #000" textLength="97.96139999999986" x="438.6000000000001" y="65.19597999999996">Imm8[1:0] = 00b : Round nearest even</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000029pt; fill: #000" textLength="57.37379999999985" x="341.58" y="71.49598000000003">Round Select: Imm8[2]</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000029pt; fill: #000" textLength="108.87119999999982" x="223.56" y="72.39598000000001">Imm8[3] = 0b : Use MXCSR exception mask</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000029pt; fill: #000" textLength="119.8158" x="81.54000000000008" y="74.67597999999998">Imm8[7:4] : Number of fixed points to preserve</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000029pt; fill: #000" textLength="78.48359999999985" x="438.6000000000001" y="75.03598">Imm8[1:0] = 01b : Round down</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000029pt; fill: #000" textLength="75.62339999999995" x="341.58" y="81.33598000000006">Imm8[2] = 0b : Use Imm8[1:0]</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000029pt; fill: #000" textLength="61.77899999999994" x="223.56" y="82.23598000000004">Imm8[3] = 1b : Suppress</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000029pt; fill: #000" textLength="70.73160000000013" x="438.6000000000001" y="84.81597999999997">Imm8[1:0] = 10b : Round up</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000029pt; fill: #000" textLength="67.66859999999991" x="341.58" y="91.1759800000001">Imm8[2] = 1b : Use MXCSR</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000029pt; fill: #000" textLength="69.68639999999994" x="438.6000000000001" y="94.65598">Imm8[1:0] = 11b : Truncate</text></g></svg>
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<figcaption><a href='vrndscalepd.html#fig-5-29'>Figure 5-29</a>. Imm8 Controls for VRNDSCALEPD/SD/PS/SS</figcaption></figure>
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<p>Handling of special case of input values are listed in <a href='vrndscalepd.html#tbl-5-31'>Table 5-31</a>.</p>
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<figure id="tbl-5-31">
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<table>
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<tr>
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<th></th>
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<th>Returned value</th></tr>
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<tr>
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<td><strong>Src1=±inf</strong></td>
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<td>Src1</td></tr>
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<tr>
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<td><strong>Src1=±NAN</strong></td>
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<td>Src1 converted to QNAN</td></tr>
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<tr>
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<td><strong>Src1=±0</strong></td>
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<td>Src1</td></tr></table>
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<figcaption><a href='vrndscalepd.html#tbl-5-31'>Table 5-31</a>. VRNDSCALEPD/SD/PS/SS Special Cases</figcaption></figure>
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<h3 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h3>
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<pre>RoundToIntegerDP(SRC[63:0], imm8[7:0]) {
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if (imm8[2] = 1)
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rounding_direction := MXCSR:RC
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; get round control from MXCSR
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else
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rounding_direction := imm8[1:0]
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; get round control from imm8[1:0]
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FI
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M := imm8[7:4] ; get the scaling factor
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case (rounding_direction)
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00: TMP[63:0] := round_to_nearest_even_integer(2<sup>M</sup>*SRC[63:0])
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01: TMP[63:0] := round_to_equal_or_smaller_integer(2<sup>M</sup>*SRC[63:0])
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10: TMP[63:0] := round_to_equal_or_larger_integer(2<sup>M</sup>*SRC[63:0])
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11: TMP[63:0] := round_to_nearest_smallest_magnitude_integer(2<sup>M</sup>*SRC[63:0])
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ESAC
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Dest[63:0] := 2<sup>-M</sup>* TMP[63:0]
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; scale down back to 2<sup>-M</sup>
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if (imm8[3] = 0) Then ; check SPE
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if (SRC[63:0] != Dest[63:0]) Then
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; check precision lost
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set_precision()
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; set #PE
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FI;
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FI;
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return(Dest[63:0])
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}
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</pre>
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<h4 id="vrndscalepd--evex-encoded-versions-">VRNDSCALEPD (EVEX encoded versions)<a class="anchor" href="#vrndscalepd--evex-encoded-versions-">
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¶
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</a></h4>
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<pre>(KL, VL) = (2, 128), (4, 256), (8, 512)
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IF *src is a memory operand*
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THEN TMP_SRC := BROADCAST64(SRC, VL, k1)
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ELSE TMP_SRC := SRC
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FI;
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FOR j := 0 TO KL-1
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i := j * 64
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IF k1[j] OR *no writemask*
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THEN DEST[i+63:i] := RoundToIntegerDP((TMP_SRC[i+63:i], imm8[7:0])
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ELSE
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IF *merging-masking* ; merging-masking
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THEN *DEST[i+63:i] remains unchanged*
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ELSE ; zeroing-masking
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DEST[i+63:i] := 0
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FI;
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FI;
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ENDFOR;
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DEST[MAXVL-1:VL] := 0
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</pre>
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<h3 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h3>
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<pre>VRNDSCALEPD __m512d _mm512_roundscale_pd( __m512d a, int imm);
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</pre>
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<pre>VRNDSCALEPD __m512d _mm512_roundscale_round_pd( __m512d a, int imm, int sae);
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</pre>
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<pre>VRNDSCALEPD __m512d _mm512_mask_roundscale_pd(__m512d s, __mmask8 k, __m512d a, int imm);
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</pre>
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<pre>VRNDSCALEPD __m512d _mm512_mask_roundscale_round_pd(__m512d s, __mmask8 k, __m512d a, int imm, int sae);
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</pre>
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<pre>VRNDSCALEPD __m512d _mm512_maskz_roundscale_pd( __mmask8 k, __m512d a, int imm);
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</pre>
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<pre>VRNDSCALEPD __m512d _mm512_maskz_roundscale_round_pd( __mmask8 k, __m512d a, int imm, int sae);
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</pre>
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<pre>VRNDSCALEPD __m256d _mm256_roundscale_pd( __m256d a, int imm);
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</pre>
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<pre>VRNDSCALEPD __m256d _mm256_mask_roundscale_pd(__m256d s, __mmask8 k, __m256d a, int imm);
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</pre>
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<pre>VRNDSCALEPD __m256d _mm256_maskz_roundscale_pd( __mmask8 k, __m256d a, int imm);
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</pre>
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<pre>VRNDSCALEPD __m128d _mm_roundscale_pd( __m128d a, int imm);
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</pre>
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<pre>VRNDSCALEPD __m128d _mm_mask_roundscale_pd(__m128d s, __mmask8 k, __m128d a, int imm);
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</pre>
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<pre>VRNDSCALEPD __m128d _mm_maskz_roundscale_pd( __mmask8 k, __m128d a, int imm);
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</pre>
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<h3 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h3>
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<p>Invalid, Precision.</p>
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<p>If SPE is enabled, precision exception is not reported (regardless of MXCSR exception mask).</p>
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<h3 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h3>
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<p>See <span class="not-imported">Table 2-46</span>, “Type E2 Class Exception Conditions.”</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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