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138 lines
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138 lines
7.2 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>VREDUCEPS
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— Perform Reduction Transformation on Packed Float32 Values</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>VREDUCEPS
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— Perform Reduction Transformation on Packed Float32 Values</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>EVEX.128.66.0F3A.W0 56 /r ib VREDUCEPS xmm1 {k1}{z}, xmm2/m128/m32bcst, imm8</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512VL AVX512DQ</td>
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<td>Perform reduction transformation on packed single-precision floating-point values in xmm2/m128/m32bcst by subtracting a number of fraction bits specified by the imm8 field. Stores the result in xmm1 register under writemask k1.</td></tr>
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<tr>
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<td>EVEX.256.66.0F3A.W0 56 /r ib VREDUCEPS ymm1 {k1}{z}, ymm2/m256/m32bcst, imm8</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512VL AVX512DQ</td>
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<td>Perform reduction transformation on packed single-precision floating-point values in ymm2/m256/m32bcst by subtracting a number of fraction bits specified by the imm8 field. Stores the result in ymm1 register under writemask k1.</td></tr>
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<tr>
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<td>EVEX.512.66.0F3A.W0 56 /r ib VREDUCEPS zmm1 {k1}{z}, zmm2/m512/m32bcst{sae}, imm8</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512DQ</td>
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<td>Perform reduction transformation on packed single-precision floating-point values in zmm2/m512/m32bcst by subtracting a number of fraction bits specified by the imm8 field. Stores the result in zmm1 register under writemask k1.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple Type</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>Full</td>
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<td>ModRM:reg (w)</td>
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<td>ModRM:r/m (r)</td>
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<td>imm8</td>
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<td>N/A</td></tr></table>
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<h3 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h3>
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<p>Perform reduction transformation of the packed binary encoded single-precision floating-point values in the source operand (the second operand) and store the reduced results in binary floating-point format to the destination operand (the first operand) under the writemask k1.</p>
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<p>The reduction transformation subtracts the integer part and the leading M fractional bits from the binary floating-point source value, where M is a unsigned integer specified by imm8[7:4], see <a href='vreducepd.html#fig-5-28'>Figure 5-28</a>. Specifically, the reduction transformation can be expressed as:</p>
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<p>dest = src – (ROUND(2<sup>M</sup>*src))*2<sup>-M</sup>;</p>
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<p>where “Round()” treats “src”, “2<sup>M</sup>”, and their product as binary floating-point numbers with normalized significand and biased exponents.</p>
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<p>The magnitude of the reduced result can be expressed by considering src= 2<sup>p</sup>*man2,</p>
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<p>where ‘man2’ is the normalized significand and ‘p’ is the unbiased exponent</p>
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<p>Then if RC = RNE: 0<=|Reduced Result|<=2<sup>p-M-1</sup></p>
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<p>Then if RC ≠ RNE: 0<=|Reduced Result|<2<sup>p-M</sup></p>
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<p>This instruction might end up with a precision exception set. However, in case of SPE set (i.e., Suppress Precision Exception, which is imm8[3]=1), no precision exception is reported.</p>
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<p>EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.</p>
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<p>Handling of special case of input values are listed in <a href='vreducepd.html#tbl-5-29'>Table 5-29</a>.</p>
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<h3 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h3>
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<pre>ReduceArgumentSP(SRC[31:0], imm8[7:0])
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{
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// Check for NaN
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IF (SRC [31:0] = NAN) THEN
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RETURN (Convert SRC[31:0] to QNaN); FI
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M := imm8[7:4]; // Number of fraction bits of the normalized significand to be subtracted
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RC := imm8[1:0];// Round Control for ROUND() operation
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RC source := imm[2];
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SPE := imm[3];// Suppress Precision Exception
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TMP[31:0] := 2<sup>-M</sup> *{ROUND(2<sup>M</sup>*SRC[31:0], SPE, RC_source, RC)}; // ROUND() treats SRC and 2<sup>M</sup> as standard binary FP values
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TMP[31:0] := SRC[31:0] – TMP[31:0]; // subtraction under the same RC,SPE controls
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RETURN TMP[31:0]; // binary encoded FP with biased exponent and normalized significand
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}
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</pre>
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<h4 id="vreduceps">VREDUCEPS<a class="anchor" href="#vreduceps">
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¶
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</a></h4>
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<pre>(KL, VL) = (4, 128), (8, 256), (16, 512)
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FOR j := 0 TO KL-1
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i := j * 32
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IF k1[j] OR *no writemask* THEN
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IF (EVEX.b == 1) AND (SRC *is memory*)
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THEN DEST[i+31:i] := ReduceArgumentSP(SRC[31:0], imm8[7:0]);
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ELSE DEST[i+31:i] := ReduceArgumentSP(SRC[i+31:i], imm8[7:0]);
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FI;
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ELSE
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IF *merging-masking* ; merging-masking
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THEN *DEST[i+31:i] remains unchanged*
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ELSE ; zeroing-masking
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DEST[i+31:i] = 0
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FI;
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FI;
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ENDFOR;
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DEST[MAXVL-1:VL] := 0
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</pre>
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<h3 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h3>
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<pre>VREDUCEPS __m512 _mm512_mask_reduce_ps( __m512 a, int imm, int sae)
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</pre>
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<pre>VREDUCEPS __m512 _mm512_mask_reduce_ps(__m512 s, __mmask16 k, __m512 a, int imm, int sae)
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</pre>
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<pre>VREDUCEPS __m512 _mm512_maskz_reduce_ps(__mmask16 k, __m512 a, int imm, int sae)
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</pre>
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<pre>VREDUCEPS __m256 _mm256_mask_reduce_ps( __m256 a, int imm)
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</pre>
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<pre>VREDUCEPS __m256 _mm256_mask_reduce_ps(__m256 s, __mmask8 k, __m256 a, int imm)
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</pre>
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<pre>VREDUCEPS __m256 _mm256_maskz_reduce_ps(__mmask8 k, __m256 a, int imm)
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</pre>
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<pre>VREDUCEPS __m128 _mm_mask_reduce_ps( __m128 a, int imm)
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</pre>
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<pre>VREDUCEPS __m128 _mm_mask_reduce_ps(__m128 s, __mmask8 k, __m128 a, int imm)
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</pre>
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<pre>VREDUCEPS __m128 _mm_maskz_reduce_ps(__mmask8 k, __m128 a, int imm)
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</pre>
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<h3 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h3>
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<p>Invalid, Precision.</p>
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<p>If SPE is enabled, precision exception is not reported (regardless of MXCSR exception mask).</p>
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<h3 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h3>
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<p>See <span class="not-imported">Table 2-46</span>, “Type E2 Class Exception Conditions”; additionally:</p>
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<table>
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<tr>
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<td>#UD</td>
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<td>If EVEX.vvvv != 1111B.</td></tr></table><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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