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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>VREDUCEPH
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— Perform Reduction Transformation on Packed FP16 Values</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>VREDUCEPH
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— Perform Reduction Transformation on Packed FP16 Values</h1>
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<table>
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<tr>
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<th> Instruction En bit Mode Flag
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Support Instruction En bit Mode Flag
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Support 64/32 CPUID Feature Instruction En bit Mode Flag CPUID Feature Instruction En bit Mode Flag Op/ 64/32 CPUID Feature Instruction En bit Mode Flag 64/32 CPUID Feature Instruction En bit Mode Flag CPUID Feature Instruction En bit Mode Flag Op/ 64/32 CPUID Feature </th>
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<th></th>
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<th>Support</th>
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<th></th>
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<th>Description</th></tr>
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<tr>
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<td>EVEX.128.NP.0F3A.W0 56 /r /ib VREDUCEPH xmm1{k1}{z}, xmm2/m128/m16bcst, imm8</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512-FP16 AVX512VL</td>
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<td>Perform reduction transformation on packed FP16 values in xmm2/m128/m16bcst by subtracting a number of fraction bits specified by the imm8 field. Store the result in xmm1 subject to writemask k1.</td></tr>
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<tr>
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<td>EVEX.256.NP.0F3A.W0 56 /r /ib VREDUCEPH ymm1{k1}{z}, ymm2/m256/m16bcst, imm8</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512-FP16 AVX512VL</td>
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<td>Perform reduction transformation on packed FP16 values in ymm2/m256/m16bcst by subtracting a number of fraction bits specified by the imm8 field. Store the result in ymm1 subject to writemask k1.</td></tr>
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<tr>
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<td>EVEX.512.NP.0F3A.W0 56 /r /ib VREDUCEPH zmm1{k1}{z}, zmm2/m512/m16bcst {sae}, imm8</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512-FP16</td>
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<td>Perform reduction transformation on packed FP16 values in zmm2/m512/m16bcst by subtracting a number of fraction bits specified by the imm8 field. Store the result in zmm1 subject to writemask k1.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>Full</td>
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<td>ModRM:reg (w)</td>
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<td>ModRM:r/m (r)</td>
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<td>imm8 (r)</td>
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<td>N/A</td></tr></table>
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<h3 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h3>
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<p>This instruction performs a reduction transformation of the packed binary encoded FP16 values in the source operand (the second operand) and store the reduced results in binary FP format to the destination operand (the first operand) under the writemask k1.</p>
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<p>The reduction transformation subtracts the integer part and the leading M fractional bits from the binary FP source value, where M is a unsigned integer specified by imm8[7:4]. Specifically, the reduction transformation can be expressed as:</p>
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<p>dest = src − (ROUND(2<sup>M</sup> * src)) * 2<sup>−M</sup></p>
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<p>where ROUND() treats src, 2<sup>M</sup>, and their product as binary FP numbers with normalized significand and biased exponents.</p>
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<p>The magnitude of the reduced result can be expressed by considering src = 2<sup>p</sup> * man2, where ‘man2’ is the normalized significand and ‘p’ is the unbiased exponent.</p>
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<p>Then if RC=RNE: 0 ≤ |ReducedResult| ≤ 2<sup>−M−1</sup>.</p>
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<p>Then if RC ≠ RNE: 0 ≤ |ReducedResult| < 2<sup>−M</sup>.</p>
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<p>This instruction might end up with a precision exception set. However, in case of SPE set (i.e., Suppress Precision Exception, which is imm8[3]=1), no precision exception is reported.</p>
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<p>This instruction may generate tiny non-zero result. If it does so, it does not report underflow exception, even if underflow exceptions are unmasked (UM flag in MXCSR register is 0).</p>
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<p>For special cases, see <a href='vreduceph.html#tbl-5-30'>Table 5-30</a>.</p>
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<figure id="tbl-5-30">
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<table>
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<tr>
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<th>Input value</th>
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<th>Round Mode</th>
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<th>Returned Value</th></tr>
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<tr>
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<td>|Src1| < 2<em><sup>−</sup></em><sup>M</sup><em><sup>−</sup></em><sup>1</sup></td>
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<td>RNE</td>
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<td>Src1</td></tr>
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<tr>
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<td rowspan="4">|Src1| < 2<em><sup>−M</sup></em></td>
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<td>RU, Src1 > 0</td>
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<td>Round(Src1 − 2<em><sup>−</sup></em><sup>M</sup>)<sup>1</sup></td></tr>
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<tr>
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<td>RU, Src1 ≤ 0</td>
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<td>Src1</td></tr>
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<tr>
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<td>RD, Src1 ≥ 0</td>
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<td>Src1</td></tr>
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<tr>
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<td>RD, Src1 < 0</td>
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<td>Round(Src1 + 2<em><sup>−</sup></em><sup>M</sup>)</td></tr>
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<tr>
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<td rowspan="2">Src1 = ±0 or Dest = ±0 (Src1 ≠ ∞)</td>
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<td>NOT RD</td>
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<td>+0.0</td></tr>
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<tr>
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<td>RD</td>
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<td>−0.0</td></tr>
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<tr>
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<td>Src1 = ±∞</td>
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<td>Any</td>
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<td>+0.0</td></tr>
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<tr>
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<td>Src1 = ±NAN</td>
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<td>Any</td>
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<td>QNaN (Src1)</td></tr></table>
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<figcaption><a href='vreduceph.html#tbl-5-30'>Table 5-30</a>. VREDUCEPH/VREDUCESH Special Cases</figcaption></figure>
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<blockquote>
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<p>1. The Round(.) function uses rounding controls specified by (imm8[2]? MXCSR.RC: imm8[1:0]).</p></blockquote>
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<h3 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h3>
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<pre>def reduce_fp16(src, imm8):
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nan := (src.exp = 0x1F) and (src.fraction != 0)
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if nan:
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return QNAN(src)
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m := imm8[7:4]
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rc := imm8[1:0]
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rc_source := imm8[2]
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spe := imm[3] // suppress precision exception
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tmp := 2^(-m) * ROUND(2^m * src, spe, rc_source, rc)
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tmp := src - tmp // using same RC, SPE controls
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return tmp
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</pre>
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<h4 id="vreduceph-dest-k1---src--imm8">VREDUCEPH dest{k1}, src, imm8<a class="anchor" href="#vreduceph-dest-k1---src--imm8">
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¶
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</a></h4>
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<pre>VL = 128, 256 or 512
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KL := VL/16
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FOR i := 0 to KL-1:
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IF k1[i] or *no writemask*:
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IF SRC is memory and (EVEX.b = 1):
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tsrc := src.fp16[0]
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ELSE:
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tsrc := src.fp16[i]
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DEST.fp16[i] := reduce_fp16(tsrc, imm8)
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ELSE IF *zeroing*:
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DEST.fp16[i] := 0
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//else DEST.fp16[i] remains unchanged
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DEST[MAXVL-1:VL] := 0
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</pre>
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<h3 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h3>
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<pre>VREDUCEPH __m128h _mm_mask_reduce_ph (__m128h src, __mmask8 k, __m128h a, int imm8);
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</pre>
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<pre>VREDUCEPH __m128h _mm_maskz_reduce_ph (__mmask8 k, __m128h a, int imm8);
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</pre>
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<pre>VREDUCEPH __m128h _mm_reduce_ph (__m128h a, int imm8);
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</pre>
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<pre>VREDUCEPH __m256h _mm256_mask_reduce_ph (__m256h src, __mmask16 k, __m256h a, int imm8);
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</pre>
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<pre>VREDUCEPH __m256h _mm256_maskz_reduce_ph (__mmask16 k, __m256h a, int imm8);
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</pre>
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<pre>VREDUCEPH __m256h _mm256_reduce_ph (__m256h a, int imm8);
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</pre>
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<pre>VREDUCEPH __m512h _mm512_mask_reduce_ph (__m512h src, __mmask32 k, __m512h a, int imm8);
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</pre>
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<pre>VREDUCEPH __m512h _mm512_maskz_reduce_ph (__mmask32 k, __m512h a, int imm8);
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</pre>
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<pre>VREDUCEPH __m512h _mm512_reduce_ph (__m512h a, int imm8);
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</pre>
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<pre>VREDUCEPH __m512h _mm512_mask_reduce_round_ph (__m512h src, __mmask32 k, __m512h a, int imm8, const int sae);
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</pre>
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<pre>VREDUCEPH __m512h _mm512_maskz_reduce_round_ph (__mmask32 k, __m512h a, int imm8, const int sae);
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</pre>
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<pre>VREDUCEPH __m512h _mm512_reduce_round_ph (__m512h a, int imm8, const int sae);
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</pre>
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<h3 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h3>
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<p>Invalid, Precision.</p>
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<h3 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h3>
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<p>EVEX-encoded instruction, see <span class="not-imported">Table 2-46</span>, “Type E2 Class Exception Conditions.”</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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