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226 lines
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226 lines
15 KiB
HTML
<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>VREDUCEPD
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— Perform Reduction Transformation on Packed Float64 Values</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>VREDUCEPD
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— Perform Reduction Transformation on Packed Float64 Values</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>EVEX.128.66.0F3A.W1 56 /r ib VREDUCEPD xmm1 {k1}{z}, xmm2/m128/m64bcst, imm8</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512VL AVX512DQ</td>
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<td>Perform reduction transformation on packed double precision floating-point values in xmm2/m128/m32bcst by subtracting a number of fraction bits specified by the imm8 field. Stores the result in xmm1 register under writemask k1.</td></tr>
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<tr>
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<td>EVEX.256.66.0F3A.W1 56 /r ib VREDUCEPD ymm1 {k1}{z}, ymm2/m256/m64bcst, imm8</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512VL AVX512DQ</td>
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<td>Perform reduction transformation on packed double precision floating-point values in ymm2/m256/m32bcst by subtracting a number of fraction bits specified by the imm8 field. Stores the result in ymm1 register under writemask k1.</td></tr>
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<tr>
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<td>EVEX.512.66.0F3A.W1 56 /r ib VREDUCEPD zmm1 {k1}{z}, zmm2/m512/m64bcst{sae}, imm8</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512DQ</td>
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<td>Perform reduction transformation on double precision floating-point values in zmm2/m512/m32bcst by subtracting a number of fraction bits specified by the imm8 field. Stores the result in zmm1 register under writemask k1.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple Type</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>Full</td>
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<td>ModRM:reg (w)</td>
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<td>ModRM:r/m (r)</td>
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<td>imm8</td>
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<td>N/A</td></tr></table>
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<h3 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h3>
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<p>Perform reduction transformation of the packed binary encoded double precision floating-point values in the source operand (the second operand) and store the reduced results in binary floating-point format to the destination operand (the first operand) under the writemask k1.</p>
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<p>The reduction transformation subtracts the integer part and the leading M fractional bits from the binary floating-point source value, where M is a unsigned integer specified by imm8[7:4], see <a href='vreducepd.html#fig-5-28'>Figure 5-28</a>. Specifically, the reduction transformation can be expressed as:</p>
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<p>dest = src – (ROUND(2<sup>M</sup>*src))*2<sup>-M</sup>;</p>
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<p>where “Round()” treats “src”, “2<sup>M</sup>”, and their product as binary floating-point numbers with normalized significand and biased exponents.</p>
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<p>The magnitude of the reduced result can be expressed by considering src= 2<sup>p</sup>*man2,</p>
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<p>where ‘man2’ is the normalized significand and ‘p’ is the unbiased exponent</p>
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<p>Then if RC = RNE: 0<=|Reduced Result|<=2<sup>p-M-1</sup></p>
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<p>Then if RC ≠ RNE: 0<=|Reduced Result|<2<sup>p-M</sup></p>
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<p>This instruction might end up with a precision exception set. However, in case of SPE set (i.e., Suppress Precision Exception, which is imm8[3]=1), no precision exception is reported.</p>
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<p>EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.</p>
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<figure id="fig-5-28">
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<svg style="width: 619.0559999999999pt; height: 129.74399999999997pt" viewBox="41.54 0.0 520.88 113.11999999999998">
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<g xmlns="http://www.w3.org/2000/svg" style="fill: none; stroke: none">
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<rect height="107.10000000000001" style="fill: rgb(0%, 0%, 0%)" width="0.48001000000000005" x="44.04" y="0.5399999999999636"></rect>
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<rect height="0.47998" style="fill: rgb(0%, 0%, 0%)" width="515.88" x="44.04" y="107.64001999999998"></rect>
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<rect height="0.23999" style="fill: rgb(0%, 0%, 0%)" width="0.48001000000000005" x="279.3" y="27.60000999999997"></rect>
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<rect height="13.200000000000001" style="fill: rgb(0%, 0%, 0%)" width="0.48001000000000005" x="279.3" y="27.839999999999975"></rect>
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<path d="M 137.64000000000001 61.49999999999997 L 133.44000000000003 64.43999999999997" style="fill-rule: nonzero; stroke: rgb(0%, 0%, 0%)"></path>
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<path d="M 139.32000000000002 63.89999999999998 L 133.44000000000003 64.43999999999997 L 135.90000000000003 59.099999999999966" style="fill-rule: nonzero; stroke: rgb(0%, 0%, 0%)"></path>
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<path d="M 159.54000000000002 46.25999999999996 L 137.64000000000001 61.49999999999997" style="fill-rule: nonzero; stroke: rgb(0%, 0%, 0%)"></path>
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<path d="M 440.46000000000004 53.51999999999995 L 444.48 56.69999999999996" style="fill-rule: nonzero; stroke: rgb(0%, 0%, 0%)"></path>
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<path d="M 442.32000000000005 51.23999999999995 L 444.4800000000001 56.69999999999996 L 438.66 55.85999999999996" style="fill-rule: nonzero; stroke: rgb(0%, 0%, 0%)"></path>
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<rect height="11.76" style="fill: rgb(0%, 0%, 0%)" width="0.48001000000000005" x="327.3" y="28.73999999999998"></rect>
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<path d="M 350.46 57.059999999999974 L 351.0 62.21999999999997" style="fill-rule: nonzero; stroke: rgb(0%, 0%, 0%)"></path>
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<path d="M 353.4 56.75999999999996 L 351.0 62.21999999999997 L 347.52 57.41999999999996" style="fill-rule: nonzero; stroke: rgb(0%, 0%, 0%)"></path>
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<path d="M 348.59999999999997 40.73999999999995 L 350.46 57.059999999999945" style="fill-rule: nonzero; stroke: rgb(0%, 0%, 0%)"></path>
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<path d="M 280.68 52.97999999999999 L 276.06 55.19999999999999" style="fill-rule: nonzero; stroke: rgb(0%, 0%, 0%)"></path>
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<path d="M 281.94 55.619999999999976 L 276.06 55.19999999999999 L 279.36 50.339999999999975" style="fill-rule: nonzero; stroke: rgb(0%, 0%, 0%)"></path>
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<path d="M 302.52 42.23999999999998 L 280.68 52.97999999999999" style="fill-rule: nonzero; stroke: rgb(0%, 0%, 0%)"></path>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000001pt; fill: #000" textLength="49.829999999999984" x="394.86" y="23.855999999999966">10</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000001pt; fill: #000" textLength="14.071200000000005" x="62.58000000000004" y="36.03599999999997">imm8</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000001pt; fill: #000" textLength="6.602400000000046" x="297.6" y="37.23599999999996">SP</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000001pt; fill: #000" textLength="41.36760000000004" x="307.35240000000005" y="37.23599999999996"> R</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.998000000000019pt; fill: #000" textLength="98.74019999999996" x="351.90600000000006" y="37.71599999999998"> Round Control Override</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000001pt; fill: #000" textLength="46.021199999999965" x="164.58000000000004" y="37.71599999999998">Fixed point length</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000001pt; fill: #000" textLength="98.29080000000008" x="224.04" y="62.61599999999996">Suppress Precision Exception: Imm8[3]</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000001pt; fill: #000" textLength="97.96980000000008" x="439.08000000000004" y="65.19599999999997">Imm8[1:0] = 00b : Round nearest even</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000001pt; fill: #000" textLength="57.37379999999985" x="342.12" y="71.55599999999995">Round Select: Imm8[2]</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000001pt; fill: #000" textLength="108.87119999999979" x="224.04" y="72.39599999999996">Imm8[3] = 0b : Use MXCSR exception mask</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000001pt; fill: #000" textLength="118.37339999999998" x="82.08000000000004" y="74.73599999999996">Imm8[7:4] : Number of fixed points to subtract</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000001pt; fill: #000" textLength="78.48359999999991" x="439.08000000000004" y="75.03599999999997">Imm8[1:0] = 01b : Round down</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.5179999999999865pt; fill: #000" textLength="75.62339999999995" x="342.12" y="81.39599999999997">Imm8[2] = 0b : Use Imm8[1:0]</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.5179999999999865pt; fill: #000" textLength="61.77899999999991" x="224.04" y="82.23599999999998">Imm8[3] = 1b : Suppress</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.5179999999999865pt; fill: #000" textLength="70.73160000000013" x="439.08000000000004" y="84.87599999999999">Imm8[1:0] = 10b : Round up</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000001pt; fill: #000" textLength="67.66259999999977" x="342.12" y="91.23599999999998">Imm8[2] = 1b : Use MXCSR</text>
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<text lengthAdjust="spacingAndGlyphs" style="font-size: 7.518000000000001pt; fill: #000" textLength="69.68579999999992" x="439.08000000000004" y="94.716">Imm8[1:0] = 11b : Truncate</text></g></svg>
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<figcaption><a href='vreducepd.html#fig-5-28'>Figure 5-28</a>. Imm8 Controls for VREDUCEPD/SD/PS/SS</figcaption></figure>
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<p>Handling of special case of input values are listed in <a href='vreducepd.html#tbl-5-29'>Table 5-29</a>.</p>
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<figure id="tbl-5-29">
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<table>
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<tr>
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<th></th>
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<th>Round Mode</th>
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<th>Returned value</th></tr>
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<tr>
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<td>|Src1| < 2<sup>-M-1</sup></td>
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<td>RNE</td>
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<td>Src1</td></tr>
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<tr>
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<td rowspan="4">|Src1| < 2<sup>-M</sup></td>
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<td>RPI, Src1 > 0</td>
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<td>Round (Src1-2<sup>-M</sup>) *</td></tr>
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<tr>
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<td>RPI, Src1 ≤ 0</td>
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<td>Src1</td></tr>
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<tr>
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<td>RNI, Src1 ≥ 0</td>
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<td>Src1</td></tr>
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<tr>
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<td>RNI, Src1 < 0</td>
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<td>Round (Src1+2<sup>-M</sup>) *</td></tr>
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<tr>
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<td rowspan="2">Src1 = ±0, or Dest = ±0 (Src1!=INF)</td>
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<td>NOT RNI</td>
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<td>+0.0</td></tr>
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<tr>
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<td>RNI</td>
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<td>-0.0</td></tr>
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<tr>
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<td>Src1 = ±INF</td>
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<td>any</td>
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<td>+0.0</td></tr>
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<tr>
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<td>Src1= ±NAN</td>
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<td>n/a</td>
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<td>QNaN(Src1)</td></tr></table>
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<figcaption><a href='vreducepd.html#tbl-5-29'>Table 5-29</a>. VREDUCEPD/SD/PS/SS Special Cases</figcaption></figure>
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<p>* Round control = (imm8.MS1)? MXCSR.RC: imm8.RC</p>
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<h3 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h3>
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<pre>ReduceArgumentDP(SRC[63:0], imm8[7:0])
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{
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// Check for NaN
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IF (SRC [63:0] = NAN) THEN
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RETURN (Convert SRC[63:0] to QNaN); FI;
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M := imm8[7:4]; // Number of fraction bits of the normalized significand to be subtracted
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RC := imm8[1:0];// Round Control for ROUND() operation
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RC source := imm[2];
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SPE := imm[3];// Suppress Precision Exception
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TMP[63:0] := 2<sup>-M</sup> *{ROUND(2<sup>M</sup>*SRC[63:0], SPE, RC_source, RC)}; // ROUND() treats SRC and 2<sup>M</sup> as standard binary FP values
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TMP[63:0] := SRC[63:0] – TMP[63:0]; // subtraction under the same RC,SPE controls
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RETURN TMP[63:0]; // binary encoded FP with biased exponent and normalized significand
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}
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</pre>
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<h4 id="vreducepd">VREDUCEPD<a class="anchor" href="#vreducepd">
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¶
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</a></h4>
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<pre>(KL, VL) = (2, 128), (4, 256), (8, 512)
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FOR j := 0 TO KL-1
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i := j * 64
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IF k1[j] OR *no writemask* THEN
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IF (EVEX.b == 1) AND (SRC *is memory*)
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THEN DEST[i+63:i] := ReduceArgumentDP(SRC[63:0], imm8[7:0]);
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ELSE DEST[i+63:i] := ReduceArgumentDP(SRC[i+63:i], imm8[7:0]);
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FI;
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ELSE
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IF *merging-masking* ; merging-masking
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THEN *DEST[i+63:i] remains unchanged*
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ELSE
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; zeroing-masking
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DEST[i+63:i] = 0
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FI;
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FI;
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ENDFOR;
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DEST[MAXVL-1:VL] := 0
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</pre>
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<h3 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h3>
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<pre>VREDUCEPD __m512d _mm512_mask_reduce_pd( __m512d a, int imm, int sae)
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</pre>
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<pre>VREDUCEPD __m512d _mm512_mask_reduce_pd(__m512d s, __mmask8 k, __m512d a, int imm, int sae)
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</pre>
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<pre>VREDUCEPD __m512d _mm512_maskz_reduce_pd(__mmask8 k, __m512d a, int imm, int sae)
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</pre>
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<pre>VREDUCEPD __m256d _mm256_mask_reduce_pd( __m256d a, int imm)
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</pre>
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<pre>VREDUCEPD __m256d _mm256_mask_reduce_pd(__m256d s, __mmask8 k, __m256d a, int imm)
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</pre>
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<pre>VREDUCEPD __m256d _mm256_maskz_reduce_pd(__mmask8 k, __m256d a, int imm)
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</pre>
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<pre>VREDUCEPD __m128d _mm_mask_reduce_pd( __m128d a, int imm)
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</pre>
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<pre>VREDUCEPD __m128d _mm_mask_reduce_pd(__m128d s, __mmask8 k, __m128d a, int imm)
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</pre>
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<pre>VREDUCEPD __m128d _mm_maskz_reduce_pd(__mmask8 k, __m128d a, int imm)
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</pre>
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<h3 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h3>
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<p>Invalid, Precision.</p>
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<p>If SPE is enabled, precision exception is not reported (regardless of MXCSR exception mask).</p>
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<h3 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h3>
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<p>See <span class="not-imported">Table 2-46</span>, “Type E2 Class Exception Conditions.”</p>
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<p>Additionally:</p>
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<table>
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<tr>
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<td>#UD</td>
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<td>If EVEX.vvvv != 1111B.</td></tr></table><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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