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<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>VPCONFLICTD/VPCONFLICTQ
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— Detect Conflicts Within a Vector of Packed Dword/Qword Values Into DenseMemory/ Register</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>VPCONFLICTD/VPCONFLICTQ
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— Detect Conflicts Within a Vector of Packed Dword/Qword Values Into DenseMemory/ Register</h1>
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<table>
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<tr>
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<th>Opcode/Instruction</th>
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<th>Op/En</th>
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<th>64/32 bit Mode Support</th>
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<th>CPUID Feature Flag</th>
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<th>Description</th></tr>
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<tr>
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<td>EVEX.128.66.0F38.W0 C4 /r VPCONFLICTD xmm1 {k1}{z}, xmm2/m128/m32bcst</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512VL AVX512CD</td>
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<td>Detect duplicate double-word values in xmm2/m128/m32bcst using writemask k1.</td></tr>
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<tr>
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<td>EVEX.256.66.0F38.W0 C4 /r VPCONFLICTD ymm1 {k1}{z}, ymm2/m256/m32bcst</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512VL AVX512CD</td>
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<td>Detect duplicate double-word values in ymm2/m256/m32bcst using writemask k1.</td></tr>
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<tr>
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<td>EVEX.512.66.0F38.W0 C4 /r VPCONFLICTD zmm1 {k1}{z}, zmm2/m512/m32bcst</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512CD</td>
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<td>Detect duplicate double-word values in zmm2/m512/m32bcst using writemask k1.</td></tr>
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<tr>
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<td>EVEX.128.66.0F38.W1 C4 /r VPCONFLICTQ xmm1 {k1}{z}, xmm2/m128/m64bcst</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512VL AVX512CD</td>
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<td>Detect duplicate quad-word values in xmm2/m128/m64bcst using writemask k1.</td></tr>
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<tr>
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<td>EVEX.256.66.0F38.W1 C4 /r VPCONFLICTQ ymm1 {k1}{z}, ymm2/m256/m64bcst</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512VL AVX512CD</td>
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<td>Detect duplicate quad-word values in ymm2/m256/m64bcst using writemask k1.</td></tr>
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<tr>
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<td>EVEX.512.66.0F38.W1 C4 /r VPCONFLICTQ zmm1 {k1}{z}, zmm2/m512/m64bcst</td>
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<td>A</td>
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<td>V/V</td>
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<td>AVX512CD</td>
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<td>Detect duplicate quad-word values in zmm2/m512/m64bcst using writemask k1.</td></tr></table>
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<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
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¶
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</a></h2>
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<table>
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<tr>
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<th>Op/En</th>
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<th>Tuple Type</th>
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<th>Operand 1</th>
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<th>Operand 2</th>
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<th>Operand 3</th>
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<th>Operand 4</th></tr>
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<tr>
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<td>A</td>
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<td>Full</td>
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<td>ModRM:reg (w)</td>
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<td>ModRM:r/m (r)</td>
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<td>N/A</td>
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<td>N/A</td></tr></table>
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<h3 id="description">Description<a class="anchor" href="#description">
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¶
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</a></h3>
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<p>Test each dword/qword element of the source operand (the second operand) for equality with all other elements in the source operand closer to the least significant element. Each element’s comparison results form a bit vector, which is then zero extended and written to the destination according to the writemask.</p>
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<p>EVEX.512 encoded version: The source operand is a ZMM register, a 512-bit memory location, or a 512-bit vector broadcasted from a 32/64-bit memory location. The destination operand is a ZMM register, conditionally updated using writemask k1.</p>
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<p>EVEX.256 encoded version: The source operand is a YMM register, a 256-bit memory location, or a 256-bit vector broadcasted from a 32/64-bit memory location. The destination operand is a YMM register, conditionally updated using writemask k1.</p>
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<p>EVEX.128 encoded version: The source operand is a XMM register, a 128-bit memory location, or a 128-bit vector broadcasted from a 32/64-bit memory location. The destination operand is a XMM register, conditionally updated using writemask k1.</p>
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<p>EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.</p>
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<h3 id="operation">Operation<a class="anchor" href="#operation">
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¶
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</a></h3>
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<h4 id="vpconflictd">VPCONFLICTD<a class="anchor" href="#vpconflictd">
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¶
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</a></h4>
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<pre>(KL, VL) = (4, 128), (8, 256), (16, 512)
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FOR j := 0 TO KL-1
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i := j*32
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IF MaskBit(j) OR *no writemask*THEN
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FOR k := 0 TO j-1
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m := k*32
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IF ((SRC[i+31:i] = SRC[m+31:m])) THEN
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DEST[i+k] := 1
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ELSE
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DEST[i+k] := 0
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FI
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ENDFOR
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DEST[i+31:i+j] := 0
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ELSE
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IF *merging-masking* THEN
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*DEST[i+31:i] remains unchanged*
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ELSE
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DEST[i+31:i] := 0
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FI
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FI
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ENDFOR
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DEST[MAXVL-1:VL] := 0
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</pre>
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<h4 id="vpconflictq">VPCONFLICTQ<a class="anchor" href="#vpconflictq">
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¶
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</a></h4>
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<pre>(KL, VL) = (2, 128), (4, 256), (8, 512)
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FOR j := 0 TO KL-1
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i := j*64
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IF MaskBit(j) OR *no writemask*THEN
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FOR k := 0 TO j-1
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m := k*64
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IF ((SRC[i+63:i] = SRC[m+63:m])) THEN
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DEST[i+k] := 1
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ELSE
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DEST[i+k] := 0
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FI
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ENDFOR
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DEST[i+63:i+j] := 0
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ELSE
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IF *merging-masking* THEN
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*DEST[i+63:i] remains unchanged*
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ELSE
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DEST[i+63:i] := 0
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FI
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FI
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ENDFOR
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DEST[MAXVL-1:VL] := 0
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</pre>
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<h3 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
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¶
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</a></h3>
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<pre>VPCONFLICTD __m512i _mm512_conflict_epi32( __m512i a);
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</pre>
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<pre>VPCONFLICTD __m512i _mm512_mask_conflict_epi32(__m512i s, __mmask16 m, __m512i a);
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</pre>
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<pre>VPCONFLICTD __m512i _mm512_maskz_conflict_epi32(__mmask16 m, __m512i a);
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</pre>
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<pre>VPCONFLICTQ __m512i _mm512_conflict_epi64( __m512i a);
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</pre>
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<pre>VPCONFLICTQ __m512i _mm512_mask_conflict_epi64(__m512i s, __mmask8 m, __m512i a);
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</pre>
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<pre>VPCONFLICTQ __m512i _mm512_maskz_conflict_epi64(__mmask8 m, __m512i a);
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</pre>
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<pre>VPCONFLICTD __m256i _mm256_conflict_epi32( __m256i a);
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</pre>
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<pre>VPCONFLICTD __m256i _mm256_mask_conflict_epi32(__m256i s, __mmask8 m, __m256i a);
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</pre>
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<pre>VPCONFLICTD __m256i _mm256_maskz_conflict_epi32(__mmask8 m, __m256i a);
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</pre>
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<pre>VPCONFLICTQ __m256i _mm256_conflict_epi64( __m256i a);
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</pre>
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<pre>VPCONFLICTQ __m256i _mm256_mask_conflict_epi64(__m256i s, __mmask8 m, __m256i a);
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</pre>
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<pre>VPCONFLICTQ __m256i _mm256_maskz_conflict_epi64(__mmask8 m, __m256i a);
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</pre>
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<pre>VPCONFLICTD __m128i _mm_conflict_epi32( __m128i a);
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</pre>
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<pre>VPCONFLICTD __m128i _mm_mask_conflict_epi32(__m128i s, __mmask8 m, __m128i a);
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</pre>
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<pre>VPCONFLICTD __m128i _mm_maskz_conflict_epi32(__mmask8 m, __m128i a);
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</pre>
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<pre>VPCONFLICTQ __m128i _mm_conflict_epi64( __m128i a);
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</pre>
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<pre>VPCONFLICTQ __m128i _mm_mask_conflict_epi64(__m128i s, __mmask8 m, __m128i a);
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</pre>
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<pre>VPCONFLICTQ __m128i _mm_maskz_conflict_epi64(__mmask8 m, __m128i a);
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</pre>
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<h3 class="exceptions" id="simd-floating-point-exceptions">SIMD Floating-Point Exceptions<a class="anchor" href="#simd-floating-point-exceptions">
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¶
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</a></h3>
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<p>None</p>
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<h3 class="exceptions" id="other-exceptions">Other Exceptions<a class="anchor" href="#other-exceptions">
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¶
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</a></h3>
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<p>EVEX-encoded instruction, see <span class="not-imported">Table 2-50</span>, “Type E4NF Class Exception Conditions.”</p><footer><p>
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This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
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inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
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ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
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</p></footer></body></html>
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