drginfo/ia32-64
1
0
Fork 0
forked from NRZCode/ia32-64
Code Pull requests Activity
ia32-64/x86/vpbroadcastb.vpbroadcastw.vpbroadcastd.vpbroadcastq.html
NRZ Code 92622c37d6 Initial commit
2025-07-08 02:23:29 -03:00

257 lines
9.8 KiB
HTML
Raw Permalink Blame History

This file contains ambiguous Unicode characters

This file contains Unicode characters that might be confused with other characters. If you think that this is intentional, you can safely ignore this warning. Use the Escape button to reveal them.

<!DOCTYPE html>
<html xmlns="http://www.w3.org/1999/xhtml" xmlns:svg="http://www.w3.org/2000/svg" xmlns:x86="http://www.felixcloutier.com/x86"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><link rel="stylesheet" type="text/css" href="style.css"></link><title>VPBROADCASTB/VPBROADCASTW/VPBROADCASTD/VPBROADCASTQ
— Load With Broadcast Integer Data From General Purpose Register</title></head><body><header><nav><ul><li><a href='index.html'>Index</a></li><li>December 2023</li></ul></nav></header><h1>VPBROADCASTB/VPBROADCASTW/VPBROADCASTD/VPBROADCASTQ
— Load With Broadcast Integer Data From General Purpose Register</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op/En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>EVEX.128.66.0F38.W0 7A /r VPBROADCASTB xmm1 {k1}{z}, reg</td>
<td>A</td>
<td>V/V</td>
<td>AVX512VL AVX512BW</td>
<td>Broadcast an 8-bit value from a GPR to all bytes in the 128-bit destination subject to writemask k1.</td></tr>
<tr>
<td>EVEX.256.66.0F38.W0 7A /r VPBROADCASTB ymm1 {k1}{z}, reg</td>
<td>A</td>
<td>V/V</td>
<td>AVX512VL AVX512BW</td>
<td>Broadcast an 8-bit value from a GPR to all bytes in the 256-bit destination subject to writemask k1.</td></tr>
<tr>
<td>EVEX.512.66.0F38.W0 7A /r VPBROADCASTB zmm1 {k1}{z}, reg</td>
<td>A</td>
<td>V/V</td>
<td>AVX512BW</td>
<td>Broadcast an 8-bit value from a GPR to all bytes in the 512-bit destination subject to writemask k1.</td></tr>
<tr>
<td>EVEX.128.66.0F38.W0 7B /r VPBROADCASTW xmm1 {k1}{z}, reg</td>
<td>A</td>
<td>V/V</td>
<td>AVX512VL AVX512BW</td>
<td>Broadcast a 16-bit value from a GPR to all words in the 128-bit destination subject to writemask k1.</td></tr>
<tr>
<td>EVEX.256.66.0F38.W0 7B /r VPBROADCASTW ymm1 {k1}{z}, reg</td>
<td>A</td>
<td>V/V</td>
<td>AVX512VL AVX512BW</td>
<td>Broadcast a 16-bit value from a GPR to all words in the 256-bit destination subject to writemask k1.</td></tr>
<tr>
<td>EVEX.512.66.0F38.W0 7B /r VPBROADCASTW zmm1 {k1}{z}, reg</td>
<td>A</td>
<td>V/V</td>
<td>AVX512BW</td>
<td>Broadcast a 16-bit value from a GPR to all words in the 512-bit destination subject to writemask k1.</td></tr>
<tr>
<td>EVEX.128.66.0F38.W0 7C /r VPBROADCASTD xmm1 {k1}{z}, r32</td>
<td>A</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Broadcast a 32-bit value from a GPR to all doublewords in the 128-bit destination subject to writemask k1.</td></tr>
<tr>
<td>EVEX.256.66.0F38.W0 7C /r VPBROADCASTD ymm1 {k1}{z}, r32</td>
<td>A</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Broadcast a 32-bit value from a GPR to all doublewords in the 256-bit destination subject to writemask k1.</td></tr>
<tr>
<td>EVEX.512.66.0F38.W0 7C /r VPBROADCASTD zmm1 {k1}{z}, r32</td>
<td>A</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Broadcast a 32-bit value from a GPR to all doublewords in the 512-bit destination subject to writemask k1.</td></tr>
<tr>
<td>EVEX.128.66.0F38.W1 7C /r VPBROADCASTQ xmm1 {k1}{z}, r64</td>
<td>A</td>
<td>V/N.E.<sup>1</sup></td>
<td>AVX512VL AVX512F</td>
<td>Broadcast a 64-bit value from a GPR to all quadwords in the 128-bit destination subject to writemask k1.</td></tr>
<tr>
<td>EVEX.256.66.0F38.W1 7C /r VPBROADCASTQ ymm1 {k1}{z}, r64</td>
<td>A</td>
<td>V/N.E.<sup>1</sup></td>
<td>AVX512VL AVX512F</td>
<td>Broadcast a 64-bit value from a GPR to all quadwords in the 256-bit destination subject to writemask k1.</td></tr>
<tr>
<td>EVEX.512.66.0F38.W1 7C /r VPBROADCASTQ zmm1 {k1}{z}, r64</td>
<td>A</td>
<td>V/N.E.<sup>1</sup></td>
<td>AVX512F</td>
<td>Broadcast a 64-bit value from a GPR to all quadwords in the 512-bit destination subject to writemask k1.</td></tr></table>
<blockquote>
<p>1. EVEX.W in non-64 bit is ignored; the instruction behaves as if the W0 version is used.</p></blockquote>
<h2 id="instruction-operand-encoding">Instruction Operand Encoding<a class="anchor" href="#instruction-operand-encoding">
</a></h2>
<table>
<tr>
<th>Op/En</th>
<th>Tuple Type</th>
<th>Operand 1</th>
<th>Operand 2</th>
<th>Operand 3</th>
<th>Operand 4</th></tr>
<tr>
<td>A</td>
<td>Tuple1 Scalar</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>N/A</td>
<td>N/A</td></tr></table>
<h3 id="description">Description<a class="anchor" href="#description">
</a></h3>
<p>Broadcasts a 8-bit, 16-bit, 32-bit or 64-bit value from a general-purpose register (the second operand) to all the locations in the destination vector register (the first operand) using the writemask k1.</p>
<p>EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.</p>
<h3 id="operation">Operation<a class="anchor" href="#operation">
</a></h3>
<h4 id="vpbroadcastb--evex-encoded-versions-">VPBROADCASTB (EVEX encoded versions)<a class="anchor" href="#vpbroadcastb--evex-encoded-versions-">
</a></h4>
<pre>(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j := 0 TO KL-1
i := j * 8
IF k1[j] OR *no writemask*
THEN DEST[i+7:i] := SRC[7:0]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+7:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+7:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
</pre>
<h4 id="vpbroadcastw--evex-encoded-versions-">VPBROADCASTW (EVEX encoded versions)<a class="anchor" href="#vpbroadcastw--evex-encoded-versions-">
</a></h4>
<pre>(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO KL-1
i := j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] := SRC[15:0]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+15:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
</pre>
<h4 id="vpbroadcastd--evex-encoded-versions-">VPBROADCASTD (EVEX encoded versions)<a class="anchor" href="#vpbroadcastd--evex-encoded-versions-">
</a></h4>
<pre>(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] := SRC[31:0]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
</pre>
<h4 id="vpbroadcastq--evex-encoded-versions-">VPBROADCASTQ (EVEX encoded versions)<a class="anchor" href="#vpbroadcastq--evex-encoded-versions-">
</a></h4>
<pre>(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] := SRC[63:0]
ELSE
IF *merging-masking*
THEN *DEST[i+63:i] remains unchanged*
ELSE ; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
</pre>
<h3 id="intel-c-c++-compiler-intrinsic-equivalent">Intel C/C++ Compiler Intrinsic Equivalent<a class="anchor" href="#intel-c-c++-compiler-intrinsic-equivalent">
</a></h3>
<pre>VPBROADCASTB __m512i _mm512_mask_set1_epi8(__m512i s, __mmask64 k, int a);
</pre>
<pre>VPBROADCASTB __m512i _mm512_maskz_set1_epi8( __mmask64 k, int a);
</pre>
<pre>VPBROADCASTB __m256i _mm256_mask_set1_epi8(__m256i s, __mmask32 k, int a);
</pre>
<pre>VPBROADCASTB __m256i _mm256_maskz_set1_epi8( __mmask32 k, int a);
</pre>
<pre>VPBROADCASTB __m128i _mm_mask_set1_epi8(__m128i s, __mmask16 k, int a);
</pre>
<pre>VPBROADCASTB __m128i _mm_maskz_set1_epi8( __mmask16 k, int a);
</pre>
<pre>VPBROADCASTD __m512i _mm512_mask_set1_epi32(__m512i s, __mmask16 k, int a);
</pre>
<pre>VPBROADCASTD __m512i _mm512_maskz_set1_epi32( __mmask16 k, int a);
</pre>
<pre>VPBROADCASTD __m256i _mm256_mask_set1_epi32(__m256i s, __mmask8 k, int a);
</pre>
<pre>VPBROADCASTD __m256i _mm256_maskz_set1_epi32( __mmask8 k, int a);
</pre>
<pre>VPBROADCASTD __m128i _mm_mask_set1_epi32(__m128i s, __mmask8 k, int a);
</pre>
<pre>VPBROADCASTD __m128i _mm_maskz_set1_epi32( __mmask8 k, int a);
</pre>
<pre>VPBROADCASTQ __m512i _mm512_mask_set1_epi64(__m512i s, __mmask8 k, __int64 a);
</pre>
<pre>VPBROADCASTQ __m512i _mm512_maskz_set1_epi64( __mmask8 k, __int64 a);
</pre>
<pre>VPBROADCASTQ __m256i _mm256_mask_set1_epi64(__m256i s, __mmask8 k, __int64 a);
</pre>
<pre>VPBROADCASTQ __m256i _mm256_maskz_set1_epi64( __mmask8 k, __int64 a);
</pre>
<pre>VPBROADCASTQ __m128i _mm_mask_set1_epi64(__m128i s, __mmask8 k, __int64 a);
</pre>
<pre>VPBROADCASTQ __m128i _mm_maskz_set1_epi64( __mmask8 k, __int64 a);
</pre>
<pre>VPBROADCASTW __m512i _mm512_mask_set1_epi16(__m512i s, __mmask32 k, int a);
</pre>
<pre>VPBROADCASTW __m512i _mm512_maskz_set1_epi16( __mmask32 k, int a);
</pre>
<pre>VPBROADCASTW __m256i _mm256_mask_set1_epi16(__m256i s, __mmask16 k, int a);
</pre>
<pre>VPBROADCASTW __m256i _mm256_maskz_set1_epi16( __mmask16 k, int a);
</pre>
<pre>VPBROADCASTW __m128i _mm_mask_set1_epi16(__m128i s, __mmask8 k, int a);
</pre>
<pre>VPBROADCASTW __m128i _mm_maskz_set1_epi16( __mmask8 k, int a);
</pre>
<h3 class="exceptions" id="exceptions">Exceptions<a class="anchor" href="#exceptions">
</a></h3>
<p>EVEX-encoded instructions, see <span class="not-imported">Table 2-55</span>, “Type E7NM Class Exception Conditions.”</p>
<p>Additionally:</p>
<table>
<tr>
<td>#UD</td>
<td>If EVEX.vvvv != 1111B.</td></tr></table><footer><p>
This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be
inc<span style="opacity: 0.2">omp</span>lete or b<sub>r</sub>oke<sub>n</sub> in various obvious or non-obvious
ways. Refer to <a href="https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4">Intel® 64 and IA-32 Architectures Software Developer’s Manual</a> for anything serious.
</p></footer></body></html>
View git blame Copy permalink